Simply recreating the PCB information adds steps, but little else.
Assigning I/O pins has transgressed well beyond a sketch or spreadsheet, and routing these large devices requires collaboration between FPGA and PCB designers. With modern I/O routing tools, savings can be realized in layer count, trace length (and consequential signal integrity improvement), and via use.
A good starting point is automation of symbol creation and PCB schematic connectivity to streamline the FPGA pin assignment process. Designers need to proceed with caution and investigate how such automation tools affect the complete product design flow. For example, an approximate recreation of the PCB information for use by an FPGA I/O assignment tool simply adds another step and another representation of the data – without fostering design convergence. Tools that create a unique set of product-specific symbol fractures for each FPGA design should be weighed against the company’s reuse and library management goals. Recreation of an entire local symbol and schematic set with each iterated pin change can make design a data management nightmare.
Instead, an FPGA/PCB optimization process that is the same from project-to-project focuses on a centralized library structure that promotes common practices among designs, as well as design reuse. Setting up this corporate “generic” environment that creates a true FPGA/PCB symbol theme has many downstream benefits, and also allows pin reassignments to be instantly communicated in a “push-button” fashion to all members of the design team.
At the librarian level, initially all symbol fractures for an FPGA are automatically generated, tied to the physical cell and part number, installed into a centralized library, approved, and made available for all users of the FPGA. FPGA power, ground, and config pins essential to the FPGA are optimally defined by the librarian, allowing functional designers to focus efforts on optimizing the I/O pins specific to the design. This approach not only fosters reuse, but avoids further design-specific regeneration of the symbol set for each iteration.
The upfront library configuration pays off not only in reusability, but also the ease through which pin iteration steps are completed. When a pin assignment change is made to the FPGA in the board context through the FPGA optimization tool, schematics containing the symbol set for the FPGA are updated with new connectivity information, and the centralized symbols themselves remain unchanged. This ease of iteration lessens the impact of design changes late in the design cycle.
To close the design loop, optimized pinouts are written and conveyed back in the FPGA vendor’s constraints file format – where the flow was initiated – as the signal names for the functional schematic, and initial pin assignments were obtained from the HDL and constraints file. Vendor I/O rules are followed throughout the process in the I/O optimization tool to adhere to DRCs for drive strength limits, VREF, I/O banking restrictions, LVDS proximity restrictions, differential pair recognition, and allowable I/O standard settings per pin. Vendor rules must be accurate and up-to-date and require close cooperation with suppliers to gain access to new architectures and package types.
From a physical implementation standpoint, comprehensive FPGA-to-PCB optimization requires further insight into the physical BGA implementation to be truly effective. Algorithms that unravel the pin connections on the FPGA to other components in the PCB context need to consider if BGA breakout and escape pre-routes have been utilized, as these effectively change the pin ordering. In the I/O optimization tool, unraveling the rats-nest connection to the escape trace endpoints provides shorter trace lengths, fewer PCB vias, and a more routable PCB than unraveling only to the pins.
Analyzing the entire design process may show that some solutions end up adding time and effort to the current project, or because the designs cannot be readily reused, future designs do not benefit as much. Optimization of connectivity meeting both FPGA and PCB design constraints requires tools that are PCB- and FPGA-aware (as well as BGA-aware), promote FPGA–PCB design concurrency while instituting repeatable processes, and have centralized reusable device representations.