Design for Test in Low-Volume Environments Print E-mail
Written by W. Scott Fillebrown   
Friday, 29 March 2013 22:11

Grid testers are out, so how do you ensure quick and inexpensive ICT?

Testing lower-volume, high-turnover assemblies is a challenge. However, with a little planning and the right contract manufacturer, test does not need to be so complex.

For markets made up of higher technology and lower quantity assemblies, in-circuit bed-of-nails test is generally not an option due to development time and cost, not to mention the challenge associated with finding a place for a 30 to 40 mils test point. These same test points also pose significant EMI concerns for most electrical engineers. So the challenge is to find a way to test a fully populated circuit thoroughly and in a timely, cost-effective way without compromising signal integrity.

Depending on the technology, this can be as simple as making minor design changes, which can actually take place at the Gerber level, to requiring a significant revision to the board in question. First let’s conquer the simple. For analog, RF and lower-technology digital boards, straightforward flying probe test is typically the answer. The assembler would employ a dual-sided flying probe tester (Figure 1). For this approach the test engineer would simply ask the designer not to cover vias with solder mask, a simple change that can be handled at the CAM/Gerber level. Depending on test coverage, the test department may recommend adding vias, assuming the design can handle it from an electrical perspective.



If, as in a sensitive analog or RF technology board, vias are being avoided, the tester may be able to test at the solder joint. This requires the customer be open-minded about “witness marks” left behind by the tester. Harder solder – for example lead-free – will reduce this problem. This typically will result in test coverage occasionally approaching 100%.

Higher technology product can pose a much more significant challenge. This technology in this class includes high-speed digital, via in pad, blind/buried vias, and high BGA counts. The curveball here is the number of circuits that actually never see an external via, so probing the circuit is impossible. The previous advice still applies: Try to have a via exposed for every circuit. This includes ensuring they are not covered by a component or solder mask. Typically this will result in “OK” test coverage, but no one wants to be just OK!

Superior test coverage on this type of product will include the use of boundary scan (JTAG) technology. This significantly increases coverage and greatly reduces test time. Stating the obvious, this assumes the components on the board are boundary-scan capable. Assuming they are, then the five-signal boundary scan daisy chain circuit needs to be connected. Typically the electrical engineer will connect them, but not for test purposes. Instead, it will be seen as a method for programming components, not for testing. (It’s important to note the original intent of boundary scan was to test, not program; however, it is more often used for programming.)

Implementing boundary scan for test can be no different than what you are currently doing for programming. Simply connecting the chain opens up the possibility of test, a great beginning. However, it is recommended a test engineer who specializes in boundary scan test review the schematic before you begin layout. Doing so will typically yield a faster, more thorough test. Test throughput will also increase by removing all circuits tested at boundary scan from the flying probe test program. This approach used on boards with an excess of 35,000 test points resulted in 95%+ test coverage.

It is possible to have a highly tested product built in the US affordably. Amazingly, what has been outlined here requires less upfront and design work than the traditional bed-of-nails in-circuit test and can be used in all phases of development, including prototype, pilot and production runs.

W. Scott Fillebrown is president and CEO of ACD ( This e-mail address is being protected from spambots. You need JavaScript enabled to view it ). His column runs bimonthly.

Last Updated on Monday, 01 April 2013 16:19
 

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