Resolving EMI Effects in High-Speed Boards Print E-mail
Written by Patrick Carrier   
Tuesday, 04 September 2012 08:09

Design tips for avoiding problems caused by radiating PCBs.

Fast edge rates on signals coupled with the proliferation of high volumes of low-cost electronic devices have made electromagnetic interference (EMI) issues extremely common. The biggest effect EMI has on a design is that a product that doesn’t pass government requirements (FCC, for example) for radiated emissions cannot be shipped. But even if the product passes, and it is still radiating, it means reduced margins for signals and possible reliability issues – and usually increased susceptibility to outside noise as well. Most of these problems can be avoided simply by making sure all currents are traveling in a closed loop.

Return current is an often mysticized piece of electronics lore. This is probably because it involves a departure from the more intuitive notion of current traveling in a wire at DC (0Hz), to thinking of current being transferred through electromagnetic fields at higher frequencies. As depicted in Figure 1, a PCB trace will couple energy into its associated reference planes through electromagnetic fields.

Figure 1

The electrical potential of the planes does not matter. Whether a ground or a voltage plane, at any given instant, the trace will be coupling energy into its reference planes. Really, it will couple energy onto whatever are the nearest “hunks” of metal, but in most well-designed PCBs, those are usually planes. Now, if those planes happen to be the power and ground planes used by I/O buffers driving that trace, that is the best case, as it best facilitates a complete loop for the return current.

Understanding current loops. To understand the current loop in terms of circuit theory, it is best to look at a side view of the trace and its reference planes (Figure 2). If we chop up the trace into very short sections, each section will have an associated inductance and capacitance per-unit-length. As the signal travels down the section, it is effectively charging each of those LC circuits, and then moving on to the next one, charging that one, and so on. This is why trace parameters often are described as inductance per-unit-length and capacitance per-unit-length. Those inductance and capacitance values are determined by the propagation of fields between the trace and reference planes, and the values can be determined for trace structures using a field solver. In fact, field solvers are used to determine the trace impedance (which happens to be the square root of L/C) and propagation delay (the square root of L*C).

Figure 2

Using this circuit description, it is clear how current travels in a loop from the trace back onto the planes. In this case, since there are two reference planes, there are two loops in parallel. Current in the trace is usually referred to as incident current, and current in the planes is usually referred to as return current. If you were to break the trace, obviously you would not expect the signal to keep going. It is important to remember that a transmission line is a combination of a trace and its reference plane, and keeping them both in good shape will eliminate most EMI problems.

Sources of radiation. What happens if you break up the reference plane? If we consider the case of a slot in the reference plane, some of the return current will surround the slot (Figure 3). Not all of the return current will surround the slot; some of it will be radiated. It actually makes a nice slot antenna. In most PCB designs, this is, of course, unintentional and can lead to EMI issues. The best way to avoid creating unintentional antennas is to keep the return current adjacent to the trace and on the reference plane(s).

Figure 3

An even more effective antenna is created when the return current path is broken completely. This occurs when a trace crosses a split in the plane. Instead of the return current following an alternate path, most of it is radiated. This is a common situation in many PCB designs. Those who have used a 3D electromagnetic simulation tool to analyze a trace crossing a plane split and identified the associated radiation levels know it is best to avoid such a situation completely.

There are a number of ways to work around traces crossing reference plane splits. Of course, it would be best to route all signals referenced to a solid ground plane, but board thickness and cost concerns often do not allow this. However, through careful stackup planning, slower signals may be routed against power planes that will be split among multiple different voltages.

Even if this is done, it usually involves a dual stripline trace structure, which uses two reference planes for two trace layers. A trace will be more closely coupled to its nearer reference plane, allowing it to cross a split in the further reference plane. As shown in Figure 1, the return current distribution scales linearly with the distance of the trace to its reference plane. So, if a trace is four times closer to its nearer reference plane than the further plane, that plane will have four times the return current.

A common method used to minimize radiation from traces crossing plane splits is to stitch the planes together in the vicinity of the trace crossing using decoupling capacitors. This can be somewhat effective; however, it is important to note that a mounted capacitor does not act as a low impedance across a wide frequency band, so it will not eliminate the radiation issue.

Finding such issues requires manual design review of the layout or an automated design rule checking tool (Figure 4). DRCs can be automated and customized to go beyond just a simple check of a trace crossing a split, to include an understanding of return current distribution between two planes, and to check for stitching capacitors.

(Ed: To see a larger version of Figure 4, please right-click on the figure, then click on View Image and expand.)

Figure 4

Other issues can be found through automated inspection as well, such as the low-inductance connection of decoupling capacitors in the vicinity of the power and ground pins of an IC. Decoupling capacitors are needed at ICs to complete the return current loop, even if there are no splits in the plane. In Figure 2, only the piece of the current loop related to the trace and planes is shown. The rest of the loop is made up of the I/O buffer driving the trace. That buffer resides on the IC, and is connected to the trace through the chip package and pins, as well as being connected to the power and ground pins. To complete the current loop, current will flow from the power pins through the buffer onto the trace. In a 0-to-1 transition, for instance, current will flow from the power pin, through the buffer and onto the trace, then back to the power pin through the planes. If the trace is configured as in Figure 2, and located symmetrically between the two planes, half of the return current will flow into the ground plane and need to make its way back to the power pin. This is where decoupling capacitors placed at the IC permit that current to flow from the ground plane back to the power pin. That makes decoupling capacitors as essential to controlling EMI as they are for maintaining power integrity.

Elimination of EMI. EMI issues are related to both power integrity and signal integrity. An inadequately designed power distribution network will lead to radiated emissions, usually corresponding to the high-impedance points of the PDN profile. For signals, if that signal is radiating energy, that also means energy is not making it to the receiver, causing a signal integrity issue. This is usually manifested as edge degradation. Signal and power integrity issues are usually solved through analysis and subsequent design changes. Solving EMI issues involves ensuring complete current loops, which can be accomplished through careful inspection of the board.

Patrick Carrier is product manager for high-speed PCB analysis tools at Mentor Graphics (mentor.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Mentor will be exhibiting in September at PCB West 2012 at the Santa Clara (CA) Convention Center.

Last Updated on Wednesday, 05 September 2012 14:48
 

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