A common signal encountering the asymmetry that created it can cause noise.
Those familiar with designing high-speed single-ended interconnects don’t have a huge leap to design high-speed differential pairs. Both types of interconnects require controlled impedance, minimized discontinuities, low loss and short stubs.
But, one important new problem can arise in differential pairs that has no comparable effect in single-ended interconnects. This new problem can completely swamp the differential signal at the receiver and can make the difference between a robust product and one that works with boards from some vendors but not others. We call this new effect “mode conversion,” and it is related to the nature of signals on differential pairs.
It takes two transmission lines to transport a differential signal. We call the combination of the two transmission lines a differential pair. The differential driver that drives a signal on a differential pair has two output pins that create two different voltages on each of the two signal lines, with respect to their common return path.
These two independent voltage signals are usually denoted by either V1 and V2 or by Vp and Vn or by V+ and V-. They are the voltages between the signal line and the adjacent return path on each line.
For example, Figure 1 shows two voltage levels for an LVDS-type signal. Voltage coming off the two signal pins of the LVDS differential driver is called a differential signal, but this is a lie. Not all the signal is a differential signal: There also is a large common signal component.
By definition, the differential signal component is the voltage difference between V1 and V2. The common signal is the average value of the voltage. When we apply these two definitions to the LVDS signal, we see the differential component has a very simple form, and, in this case, a common signal is present, but constant.
If the two signals, V1 and V2, are perfectly symmetric – the same values, but exactly opposite – the average value will always be constant, and there will be no modulated common signal. If there is any asymmetry in the two voltages that make up the two signals, either in their voltage levels or their relative timing, some of the differential signal will be transformed into common signal. This effect is mode conversion: any asymmetry of any sort between the two signals that creates common signal and distorts the differential signal. This can arise from asymmetry in the driver or asymmetry between the two lines that make up the interconnect.
No amount of distortion of the differential signal path will cause mode conversion, provided whatever is done to one line is done to the other. Of course, the differential signal could be grossly screwed up, but if so, there will be no mode conversion.
A difference in the cross-section between the two lines that make up the differential pair would change the impedance the driver sees looking into each of the two lines, and this would affect the voltages launched into the lines and generate common signal.
The most common source of asymmetry is a length difference between the two lines that make up a differential pair. It’s very easy to explore the effects of a length asymmetry on a differential signal using any circuit simulator that can perform a little algebra to show the calculated differential and common components of the signal (Figure 2).
As the length difference increases, the differential signal is degraded and a common signal is created. The most important problem with mode conversion is that the differential signal is degraded. Any length difference between the two lines in the pair will cause a time delay skew between them, resulting in some conversion of differential to common signal. And, this happens at the edges of the signal, which will directly impact the shape of the eye diagram.
A possible problem with the common signal arises if it were to get outside the enclosure of the product, on external, unshielded twisted pairs. It only takes about 3 µA of common current on external cables to fail an FCC Class B certification test. Less than 1 mV of common signal on an external unshielded cable will fail this test. That’s why every RJ45 connector to a cat 5 cable uses a common signal choke to dramatically attenuate common signals before they can be launched onto unshielded cable. However, if the common signal does not get out of the enclosure, it will rarely have an EMI impact. After all, every single-ended trace on a circuit board has a huge common signal without causing EMI issues.
Impact on Eyes from Mode Conversion
A more important secondary problem with mode conversion is that there will now be some common signal rattling along the differential pair. If it is not terminated, this common signal will reflect back and forth between the ends of the line. Since the receiver is sensitive to only the differential signal, rarely will the common signal cause a problem for the receiver.
However, if this common signal, in reflecting up and down the line, encounters the same asymmetry that created it, some of this common signal may convert back into differential signal, and this new differential signal, asynchronous with the initial differential signal, will be picked up by the receiver and look like random noise.
Figure 3 shows the impact on a 5 Gbps PRBS eye for different line-to-line skews for the two cases of the common signal terminated and not terminated. When it is not terminated, the differential noise increases over the entire eye. When the common signal is terminated, it will not rattle around and will not contribute to asynchronous differential noise.
Terminating the common signal does nothing to prevent mode conversion and the distorting of the differential signal; it just keeps the reflecting common signal from distorting it further. Terminating the common signal will result in a cleaner eye, and the same amount of mode conversion will have less impact with a terminated common signal than without.
In all high-speed serial links, it is critical to terminate the differential signal, and this is always done with a resistor across the far end of the differential pair. The common signal, when reaching this far end resistor, will still see an open and reflect. To terminate both the differential signal and the common signal requires not one resistor but three (Figure 4).
To terminate the differential signal at the far end, R1 must be the odd mode impedance of the differential pair, typically close to 50Ω. To terminate the common signal at the end of the line, the parallel combination of the two R1 resistors in the series with R2 must be the impedance the common signal sees. After a little algebra, the value of R2 is found to be 0.5 x (Zeven – Zodd).
In loosely coupled pairs, the difference between the even and odd mode impedances is very small, so R2 is on the order of 1 to 5Ω. With this resistor network, the drivers will see an impedance of about 25Ω to the return path for the common signal. This will often mean a very high power dissipation, disastrous in many applications.
To prevent the DC power consumption but still provide an adequate termination for the common signal, a DC blocking capacitor is often placed between the center tap of the resistors and the return of the common signals. This network will terminate both the common signal and the differential signal. The implementation of this network and the resulting eye of a 1 Gbps PRBS signal with and without the common signal terminated are shown in Figure 5.
If there is so much asymmetry to distort the differential signal to worry about terminating the common signal, the way to fix this problem is to first eliminate the asymmetry at the source, then worry about terminating the common signal.
Too Much Skew?
Do not confuse line-to-line skew in a differential pair with jitter in the eye diagram. They are not the same. In fact, even when the skew is as long as 10% the unit interval, the impact on jitter in the eye is barely discernable.
It is common for high-speed signaling protocols to set a limit on the total acceptable line-to-line skew in a channel as less than 10% the unit interval. This includes all sources of skew, such as in the driver, the packages, the connectors, cables and the circuit board traces.
For a 1 Gbps signal, the unit interval is 1 nsec and a total skew spec might be 0.1 nsec. If this is all due to a length difference, using roughly 6 in/nsec as the speed of a signal, this suggests the total length difference that could be tolerated is 0.6 in. But, this is to be allocated to all circuit elements. If the board is allocated 10% of this total skew budget, the spec on the length matching for the board interconnects would be 0.060". As the bit rate increases, the total length skew allocated to the board would decrease.
For example, at 5 Gbps, this would be a total length skew limit of 0.012". When it is no longer free to match line lengths in a differential pair to this close a length, the skew budget would be renegotiated, or reevaluated. After all, a total skew of more than 10% the unit interval can be tolerated in many designs before the jitter becomes noticeable. At 5 Gbps, this is a length difference between the two lines in the pair of 0.120".
A second source of skew comes from the difference in speed between the signals in the two lines, as due to an asymmetrical dielectric distribution. This arises when one line in a pair sees more glass bundles than the other line and a higher Dk value, and travels slower than a signal in the other line.
This “glass weave”-induced skew is statistical in nature. It comes about due to the random chance that one line overlaps a glass bundle, while the other line in the pair sees a more resin-rich region. The magnitude of the effect depends on many uncontrollable factors, such as how well aligned the routing trace path is to the glass weave axis, the local variation in the Dk across the glass weave bundle, the pitch of the glass weave and the pitch between the two lines in the pair.
Controlling this source of mode conversion is about risk reduction. One approach is to keep your fingers crossed and hope for the best. Some designers have found this an adequate risk reduction strategy at 2.5 Gbps and hope it will also work at 5 Gbps.
Another approach is to route the two lines in a pair on the same pitch as the glass weave. In typical 1080 or 2116 glass yarn, the weave pitch is about 0.021" along one axis. Routing the two lines in a differential pair on a 0.021" pitch will increase the chance the two lines see the same local Dk environment – either both resin-rich or both glass-rich.
Yet another approach is to use a glass yarn that is more uniform (Figure 6). In this case, the Dk does not vary nearly as much over the surface of the board, and the weave induced skew is dramatically reduced.
There are routing solutions as well: Don’t route along the glass wave axis; rotate the artwork relative to the edge of the board, or route with zigzags. All these solutions are to try to decrease the change of creating glass weave-induced skew.
As with so many signal integrity effects, problems get worse as data rates increase. While 1 Gbps systems have a high tolerance for skew-induced mode conversion, a 5 Gbps system is much more sensitive. Design approaches for 1 Gbps systems may not work at 5 Gbps, and it is important to reevaluate the design processes and constraints to verify robust performance in your next system design. This is why understanding the nature of the mode conversion problem, its root cause and the solutions available in your toolbox is more important each day. As we know, as speed goes up, luck goes down, but the more you know, the luckier you get. PCD&F