White Papers

The new RoHS Directive became law on July 21, 2011.

Among the highlights: The revised directive adds no new restricted substances, and contains nine exclusion categories: military, space, transportation (trains, planes, autos), fixed installation, large industrial tools, off-road machinery (i.e., bulldozers), implantable devices, solar panels, and R&D equipment. Medical and monitoring/control equipment have three years to comply, in-vitro medical has five years, and industrial monitoring/control has six years. Exemptions will end in five to seven years for telecom and high lead products. Larger companies must go beyond certificates of compliance, and EU importers are now also liable.

"Insider Design Tips for Affordable High-Density Interconnect (HDI) PCBs"

This white paper, written for PCB layout engineers, aims to demystify HDI PCB design and show a methodical approach for increasing electrical performance, signal integrity, and manufacturability, while reducing design time, development cost, and product cost. It instructs on planning a design approach, choosing the right PCB materials, managing stack-up and microvia structures, and available tools to aid the process.

(Registration required.)

"Methodologies for Efficient FPGA Integration into PCBs"

This document helps readers to grasp how PCB design considerations play a major role in obtaining the expected performance from FPGAs. Specifically, it focuses on early analysis and simulation methodologies as a way of performing a guided implementation. That is, if variables affecting the design under development are analyzed and results passed onto the implementation tool, then it is more likely the desired design specifications will be met in the first implementation pass, fulfilling the ultimate goal to keep development effort, cost, and time to a minimum.

For a copy of the paper, click here.

 

The Low Mass Solution to 0402 Tombstoning

Tombstoning occurs when a part is pulled up on one side, assuming a vertical orientation that looks like a graveyard headstone. Suntron performed a dimensional evaluation on seven manufacturers of capacitors and six manufacturers of resistors commonly used by its customers. The analysis, which looked at the component body and its terminations, revealed was that 86% of the capacitor manufacturers and 50% of the resistor manufacturers had different body and termination dimensions and tolerances. (By comparison, a similar evaluation of the same component manufacturers' 0201 and 0603 package types showed identical parts.)

Reno says these variations in the components must be accounted for in the pad geometry, or else tombstoning may occur. He also recommends  treating each pad as a group, and ensuring the copper density of each pad is equal (or very close), meaning both pads achieve the same temperature and liquidus at the same time. Also, Reno says, both pads should achieve solder flow to exposed copper at the same time, and be equal in solder volume necessary to control capillary action.

Reno recommends a specific pad geometry for 0402a, reduces the soldermask clearance to 0.002" (from 0.005"), and suggests a connecting trace between pad and plane (or very wide trace) to be equal as the sister pad.

Author: Eric Reno, product engineer II

Parts Collaboration within The Sunstone ECOsystem

Sunstone Circuits’ technological collaboration with Digi‐Key Corp. and NXP Semiconductor provides Sunstone PCB123 CAD users access to ready‐made, certified parts symbols from NXP. Not only is sufficient information provided to ensure accurate physical design, but the collaboration also ensures efficient design with component availability and pricing information. Within the Sunstone ECOsystemSM, these new functional elements provide the end user with a turnkey level of convenience and accuracy, even when working on prototypes and early engineering projects.

Authors: Keith Ackermann and Nolan Johnson, Sunstone Circuits

Backplane Architecture High Level Design

The backplane is the key component in any system architecture. The sooner one considers the backplane’s physical architecture near the beginning of a project, the more successful the project will be. This white paper introduces the concept of a backplane High Level Design document and demonstrates the principle using a fictitious system architecture as an example.

Author: Bert Simonovich, Jan. 2011

Backplane Architecture High Level Design Slides: Example of a backplane HLD document slide deck used in Backplane Architecture High Level Design white paper.

Practical Fiber Weave Effect Modeling

Fiber-weave effect is becoming more of an issue as bit rates continue to sore upwards to 5GB/s and beyond. Due to the non-homogenous nature of printed circuit board laminates, the fiberglass weave pattern causes signals to propagate at different speeds within differential pair traces; causing timing skew and mode conversion at the receiver; leading to reduced bit-error-rate (BER) performance; and increased EMI radiation. This white paper delves into the issue and presents a novel approach to practically establish worst case min/max values for Dk and use them to model this effect using Agilent EEofEDA circuit modeling software. A PCIe CEM Rev2 case study is used to practically demonstrate the model and to explore the design space.

Author: Bert Simonovich

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