John McMillan

Constrain what is necessary, but don’t go overboard.

Back in the printed circuit board’s early days, before EDA tools were even necessary, constraints were handled verbally. The engineer would carry the schematic to the PCB designer and concisely state the constraints: “Can you fit this on a 4x6" board?” That’s certainly not the best way to communicate constraints, although I would guess there are instances when the design still needs little more communication than that. 

Read more: Effectively Managing PCB Design Constraints
Changing copper weight is not as simple as changing the database setting or drawing.

On power-intensive designs, PCB designers feel like Scotty from Star Trek: caught between competing demands. The engineer needs more copper to pull more amperage, but the designer has to be aware of the board fabricator’s capabilities. Applying increased copper weight to power boards is not an uncommon approach, but designs requiring a great deal of power on high-speed digital boards are becoming common. Designers now juggle the needs of high-speed design and power in one board. Increasing layers is one way to increase copper coverage, but the additional layers will increase the thickness of the board more than increased copper weight. If the finished product can handle the increased thickness, and smaller vias are not required, an option is to increase the layer count. If the vias are dictated by the component (BGA fanout or limited routing channels) or routing parameters, then increasing copper weight is an option.

Changing copper weight is not as simple as changing the database setting or fab drawing. Close communications with the fabricator are crucial in the success of the final product. Changing the copper weight increases the board thickness. The increased board thickness changes the aspect ratio of the vias.

A 62 mil board with 8 mil drills is acceptable for the majority of fabricators. Once the copper weight increases and causes the overall board thickness to increase to 80-plus mils, however, the via aspect ratio becomes a concern for some fab shops. The increased copper and increased drill affect the anti-pad for internal layers. The majority of fabricators used for the latest high amperage board wanted a minimum of 22 mils over drill for 3 oz. The increased anti-pad permits less copper to flow through via fields. If the copper is flowing through a BGA, the change in copper weight could be robbing Peter to pay Paul (Figure 1). The increase to 3 oz. reduces the copper channel between the BGA fanout. Gaining 1 oz. of copper loses 3 mils through the channel. If there are several channels through the BGA, then the decision becomes easier.

Figure 1. Increases in copper weight can distort the via aspect ratio.

Figure 1. Increases in copper weight can distort the via aspect ratio.

There are other concerns when using higher copper weights in the design. Material availability becomes an issue as copper weight increases. While 3 oz. may be a common size in the US, it might not be in another market. Once product ramps to volume, 3 oz. for production runs may not be readily available. Verify with the expected fabricator the availability and their process limits. If the end-product requires UL approval, ask the fab for the highest UL-approved copper weight. Shops are able to get higher copper weights but may not be UL-approved for higher weights.

Close communication with the fabricator will ensure an on-time, robust design. Keeping communications open and honest with the fab vendor is the shortest route to a successful build.

Noah Fenley, CID, is design manager at ACD (; This email address is being protected from spambots. You need JavaScript enabled to view it.. 

Blind, buried or smaller-sized holes can reduce plane voids and insertion loss.

High density interconnect technology can increase design density and reduce overall board size. It can also improve the signal and power integrity of a PCB. Here are two case studies that show how blind vias, buried vias and microvias can be used effectively.

Case 1: Improve power integrity by reducing voids in planes. High-power designs for high-speed digital signals require low impedance PCB power planes for proper operation. Therefore, solid planes for power and ground are always preferred. In many cases the power and ground planes under a BGA component have voids, as a result of through-hole vias. These voids have negative effects on power integrity, such as:

  • Increased plane inductance.
  • Increased plane resistance (as IR drop from power supplies to BGA pads).
  • Decreased plane capacitance.

Figure 1 shows how 8mil through-hole vias under a 0.8mm-pitch BGA have created voids in the three split power planes. The copper webs between the voids are just 3.5 mils wide. By replacing the through-hole vias with blind or microvias, the plane voids can be reduced (Figure 2).

Figure 1. Voids and split power planes under BGA component.

Figure 2. Voids eliminated with HDI technology.

Case 2: Improve signal integrity by eliminating via stubs. At speeds of 5Gbps or 2.5GHz and faster, via stubs begin to have a noticeable impact on the insertion and return loss of a PCB. Through-hole via stubs can be removed mechanically in some applications, but in the case of PTH high-speed connectors, such as backplane connectors, pins cannot be back-drilled. One solution is to use surface-mount high-speed connectors and blind vias (Figure 3).

Figure 3. Through-hole via stub, before and after.

Figure 4 shows two via stubs in both ends of a through-hole via for layer exchange of striplines. Buried vias, then, can be employed to eliminate the stubs.

Figure 4. Through-hole via stub, before and after.

In these cases, the use of blind vias and buried vias completely eliminates the through-hole via stub, improving the signal integrity of the PCB.

These are just two situations where HDI technology enables a layout designer to produce better quality PCBs. With recent advancements in PCB manufacturing capabilities, look for many more case studies to come.

Pi Zhang is a senior design engineer at Nuvation Engineering (, a design firm specializing in electronic design services and product development; This email address is being protected from spambots. You need JavaScript enabled to view it..

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