SANTA CLARA, CA – Cadence is accepting abstracts for CDNLive Silicon Valley, which will take place April 5-6.

Suggested topics for 2016 include overcoming 10nm/16nm design challenges; designing in DDR memory; analog/mixed-signal SoC verification; application-specific verification; using accelerated verification IP to simplify simulation acceleration; cross-fabric design; silicon photonics; 3D IC; low-power design and verification considerations; digital design and full-flow correlation; IoT; image/vision processing, and USB type-C solutions.

Submissions are due by Jan. 22.

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