Unwanted capacitance hanging off signal traces can cause unwanted resonances and excessive attenuation.

Data rates for very high-speed data links keep climbing. PCIExpress Gen 4 is 16Gb/s, and Gen 5 is 32Gb/s. Data rates on links in high-speed routers and servers are as high as 56Gb/S. RF engineers would call all these microwave frequencies, even though they are “just” digital. It should come as no surprise that elements that did not matter at lower data rates can have significant effects at much higher data rates. Vias are one of these.

It has been shown many times that the vias used to connect signal pins to traces on innerlayers of PCBs are visible. It has also been shown that the effects of these vias can be ignored at the clock frequencies used until the advent of very high-speed differential signaling. Much to the dismay of design engineers, at very high data rates these vias often are the source of unexpected signal degradation, often to the point of failure. Here we show examples of this degradation and where it comes from, along with methods for minimizing this degradation.

To continue reading, please log in or register using the link in the upper right corner of the page.

Submit to FacebookSubmit to Google PlusSubmit to TwitterSubmit to LinkedInPrint Article