Bandwidth Tests Reveal Shrinking Eye Diagrams and Signal Integrity Problems
Executive Summary
Factors like jitter, inter-symbol interference (ISI), crosstalk and others can create havoc on the signal integrity of high-speed serdes and memory channels, making maximum bus speeds difficult to achieve in practice. Compounding this predicament is the fact that channel speeds keep increasing from one generation bus technology to the next. With each step upward to a higher speed and higher signaling frequencies, a serdes or memory bus becomes more susceptible to distortions and anomalies which can effectively disrupt bus traffic and stall system throughput. For serdes buses like PCI Express™ , Serial ATA, USB, Intel’s QuickPath Interconnect (QPI) and memory buses like DDR, the higher the frequency of the signaling, the more susceptible the interconnect becomes to errors, re-transmissions and other anomalies.
To avoid potential problems with high-frequency bus traffic the signal integrity on the bus must be validated during each of the major phases of a system’s life cycle, including design/development, manufacturing and as an installed system in the field. If the signal integrity on a serdes channel is not what it should be, steps should be taken to correct the problem and improve system performance.
Unfortunately, effectively and economically validating the signal integrity on a high-speed bus has become more difficult as the limitations of legacy probe-based test equipment have become more obvious in recent years. Now though, non-intrusive software-driven test methods based on embedded instrumentation are providing alternative validation solutions that are more costeffective and deliver observed signal integrity data. These methods provide soft access to hard data. In addition, industry specifications like the IEEE P1687 Internal JTAG (IJTAG) standard for embedded instrumentation are emerging to simplify and streamline the adoption of signal integrity validation techniques based on embedded instruments.
