ARLINGTON, VA – JEDEC has published the JESD79-5C DDR5 SDRAM standard, which includes features designed to improve reliability and security and enhance performance in applications from high-performance servers to emerging technologies such as AI and machine learning.

JESD79-5C introduces an innovative solution to improve DRAM data integrity called Per-Row Activation Counting (PRAC). PRAC precisely counts DRAM activations on a wordline granularity. When PRAC-enabled DRAM detects an excessive number of activations, it alerts the system to pause traffic and to designate time for mitigative measures. These interrelated actions underpin PRAC's ability to provide a fundamentally accurate and predictable approach for addressing data integrity challenges through close coordination between the DRAM and the system.

Additional features offered in JESD79-5C DDR5 include:

• Expansion of timing parameters definition from 6800Mbps to 8800Mbps
• Inclusion of DRAM core timings and Tx/Rx AC timings extended up to 8800Mbps, compared to the previous version which supported only up to 6400 timing parameters and partial pieces up to 7200 DRAM core timings
• Introduction of Self-Refresh Exit Clock Sync for I/O Training Optimization
• Incorporation of DDP (Dual-Die Package) timings
• Deprecation of PASR (Partial Array Self Refresh) to address security concerns.

"I’m delighted to highlight the collaborative efforts of JEDEC’s JC-42 Committee for Solid State Memory to advance the DDR5 standard," said Mian Quddus, chairman of JEDEC's board of directors. "Groundbreaking new features in JESD79-5C are intended to support ever-evolving industry demands for security, reliability and performance in a wide range of applications."

"The JC-42 Committee is pleased to unveil PRAC, a comprehensive solution to help ensure DRAM data integrity, as an integral component of the DDR5 update. Work is underway to incorporate this feature into other DRAM product families within JEDEC,” said Christopher Cox, JC-42 committee chair.