WILSONVILLE, OR -- Mentor Graphics today announced full interoperability between the Tessent IJTAG chip-level IP integration product and Asset InterTech’s ScanWorks platform for embedded instruments, which includes chip, circuit board and system-level IJTAG tools. This combination of capabilities delivers a chip-to-system-level automated IJTAG IP integration solution said to simplify the user’s ability to leverage chip-level resources to the printed circuit board or system levels. Chip IP that is compliant with the IJTAG standard (IEEE P1687), such as self-test or diagnostic functions, can now be seamlessly accessed from board debug, validation and test systems or in the field from system software.

“In order for the IJTAG standard to be effective, system-on-a-chip (SoC) and PCB designers, as well as system-level manufacturing engineers, need an ecosystem of support from semiconductor IP providers, EDA tool providers and hardware/software debug, validation and test tool providers,” said Kent Zetterberg, Asset’s IJTAG product manager. “We’re working with Mentor to provide a seamless flow based on IJTAG from the IC design environment to the SoC and PCB debug, validation and test phase.”

“We are now seeing widespread interest in the IJTAG standard within our customer base,” said Stephen Pateras, product marketing director at Mentor Graphics. “Ensuring interoperability with key partners like ASSET will help maximize the benefit to our customers when adopting this new technology and standard. At this year’s International Test Conference, Mentor and Asset will demonstrate a design flow with full PDL/ICL interoperability to be delivered later in the year, synchronized with ratification of the IEEE P1687 IJTAG standard.”

Have you registered for PCB West, the Silicon Valley's largest printed circuit board trade show? Sept. 24-26, at the Santa Clara Convention Center. www.pcbwest.com

Tags: Mentor Graphics, Asset InterTech, Tessent, JTAG, printed circuit board design, SoC