WILSONVILLE, OR – Mentor Graphics and Tezzaron Semiconductor said they are collaborating to integrate Mentor’s Calibre 3DSTACK into Tezzaron’s 3D-IC offerings.

The integration will focus on automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies while verifying die-to-die interfaces in a separate procedure with automation features.

Tezzaron offers wafer stacking and die stacking technology with TSVs, Bi-STAR built in self-test and repair.

Complementing 3D-IC design capabilities, Calibre 3DSTACK provides DRC, LVS, and parasitic extraction (PEX) capabilities. It verifies physical offset, rotation, and scaling at the die interfaces. It enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation.

The companies plan to extend their collaboration to include development of solutions for the silicon photonics market.