MOUNTAIN VIEW, CA -- Synopsys today unveiled an initiative to accelerate the design of stacked die silicon systems using 3D-IC integration.

The EDA vendor said it is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products, to meet the requirements of faster and smaller electronic products that consume less power.

3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. 3D-IC integration uses through-silicon via (TSV) technology, an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking. The use of TSVs can increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.

"As 2D scaling becomes impractical, 3D-IC integration becomes the natural evolution of semiconductor technology; it is the convergence of performance, power and functionality," said Phil Marcoux, managing director at PPM Associates. "Some of the benefits of 3D-IC integration, such as increasing complexity, improved performance, reducing power consumption and decreasing footprints, are proven and readily understood. Other reported benefits, such as improving time-to-market, lowering risk and lowering cost, still need to be realized before 3D-IC integration becomes a commercially viable alternative to traditional 2D architectures. The availability of Synopsys' silicon-proven EDA and IP solutions is an important contribution to deploying 3D-IC integration technology in the semiconductor industry."

Stacked die are becoming common, and companies like Amkor are packaging 16 or more die in volume for Intel.

For more on TSV and its possibilities, click here and here.