SAN JOSE -- With Xilinx’s announcement of the first shipments of its Virtex-7 2000T Field Programmable Gate Array (FPGA), the era of 2.5D has begun. Xilinx reports that the 2000T is the world’s highest-capacity FPGA using 6.8 billion transistors, providing customers access to an unprecedented 2 million logic cells, equivalent to 20 million ASIC gates for system integration, ASIC replacement, and ASIC prototyping and emulation.

Co-design with packaging technology has created a new FPGA that reduces system cost and increases performance with lower power. By not having to drive off-chip I/Os across PCB traces to adjacent FPGAs, designers for high-performance applications that have previously used multiple FPGAs in their systems will be able to benefit from the high-bandwidth, low-latency, power-efficient interconnect between the FPGA die.

The key to the performance gains is the silicon interposer or what Xilinx calls its “Stacked Silicon Interconnect” technology.

Xilinx has been able to partition its die into slices that are manufactured as smaller areas on the wafer that a conventional large FPGA die. The slides are fabricated in 28 nm silicon technology. These slices are mounted on a passive silicon interposer with 10:1 aspect ration TSV fabricated on 65nm node silicon technology by TSMC. The interposer has four interconnect layers on each side of the interposer. The slices are mounted on the interposer with copper pillar microbumps. There are approximately 10,000 connections made vertically to allow chip-to-chip communication through the interposer. An additional advantage of using the interposer is the ability to control the stresses in the low-k dielectric material used to fabricate the FPGA slices. The interposer is mounted using flip chip bumps on a conventional build-up laminate substrate to complete the BGA package.

3D TSV is often touted as the way to achieve higher performance and lower power, but Xilinx has found that the use of a silicon interposer also delivers similar benefits. The 7 series FPGA families all share a unified architecture implemented on TSMC’s 28nm HPL process technology optimized for low power with high performance. This unique combination reportedly delivers 50% total power reduction and enables a 2X price/performance improvement, 2X increase in system performance and the world’s first 2 million-logic-cell FPGA (providing 2.5X higher capacity compared to previous generations). As a result, Xilinx reports that designers can easily scale their applications for system performance, capacity, or cost within and across the 28nm families while staying within power budgets.

The 20W of device power consumption and 8W are I/O power are based on power estimates (using the competitions power estimator) for a fully utilized design in the largest available monolithic device with more than 900,000 resources.  It would take four of these devices combined to equal the total DSP bandwidth possible in a single Virtex-7 2000T.

The era of silicon interposers has begun and the importance of packaging in achieving increased levels of performance is clearly recognized. In-package integration will provide major advantages for devices makers through the next generation silicon technology.

E. Jan Vardaman is president of TechSearch International (techsearchinc.com); This email address is being protected from spambots. You need JavaScript enabled to view it. and a contributing editor to PCD&F. Her column appears bimonthly.