"We are very pleased and excited that ASSET has joined our OpenDoor Program," said Greg Aldrich, marketing director at Mentor Graphics. "As the leading DFT tools supplier it is important to validate and ensure interoperability with downstream applications that our customers are using."

Initially, interoperability testing will be conducted for both the original boundary scan standard, IEEE 1149.1, as well as the newer IEEE 1149.6 standard that specifies a test methodology for high-speed, differential interconnects.

"Users of EDA tools like those from Mentor are interested in boundary scan and JTAG verification because many of the chips they are designing will include core embedded instrumentation. These embedded instruments will be accessed by JTAG, so full compliance with all boundary scan standards is needed to automate, access and analyze them," explained Alan Sguigna, ASSET’s VP of sales and marketing.