SAN JOSE — Cadence Design Systems today unveiled the Allegro 16.6 portfolio, which emphasizes faster documentation creation and high-speed designs.

"Almost every design except for pure RF or pure analog circuits has to worry about high speeds because of the chip speeds," explained Hemant Shah, director of product management for Allegro PCB, in announcing the rollout. "Any kind of DDR3 or DDR4 memory has to worry about it."

New capabilities in Allegro PCB Editor include adding ground current return path vias for differential pairs during initial point-to-point connect; creating off-angle routing quickly to avoid coupling with FR-4 fabric weave and better impedance control; improved arc support; and adjusting spacing for signals in interfaces such as DDR3 and DDR4, allowing users to compress signals in high-density route areas, and to spread signals to avoid crosstalk between signals or make space for tuning.

A new shape-editing AppMode creates and modifies complex shape geometries easily and quickly for copper shapes, flex cover lay geometries and complex pad shapes.

"Designers are trying to shorten the time to get to a routed, shielded design very quickly. With faster transfer rates like DDR4, with the differential pairs, that’s adding more time. We are trying to move away from what’s taxing them," Shah told PCD&F.

The latest release also takes steps to improve non-value added tasks like documentation. The PCB Designer Manufacturing Option is said to shorten the time to create manufacturing documentation by up to 60%. Like its OrCAD release last week, it is built on DownStream Technologies' Blueprint-PCB platform, which automates the process and streamlines handoff to manufacturing. All the documentation is provided in .pdf format.  

"The DFM Checker can set up rules based on the specific fabricator. This keeps it independent of the design," Shah said. "It is tightly integrated: The user doesn’t have to get out of PCB Editor. Once you’ve built the rule set, you are set until the fabricator changes their capability."

The Rules Developer and Checker allows users to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an OEM. Rules can be viewed and executed from the Allegro Constraint Manager, making it a single source for all design rules checks within a PCB. 

"We used RAVEL, a new relational language, which makes it easier for customers to write rules for geometric checks such as comparisons, measures, distances, and so on," Shah explained. "A lot of companies write their own rules. Here, we do it inside of Allegro. It's the same methodology; they can run the rules, look at errors, go back and revise, and it’s very easy for them to do this. It lets users extend what we offer."