EMA Design Automation introduces the TimingDesigner 9.2, which interfaces with Cadence Allegro PCB signal integrity (SI) technology.

Users are able to do a full SI and timing analysis early in the design phase, with best in class timing reporting technology to accurately manage timing paths. The graphical interface enables a review of the entire signal path, while making developing and performing analysis on complex timing relationships easy.

Features include enhanced support for SDC generation, 65 nm and below support for Altera FPGAs and a new interface to the Actel Libero development environment.

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