Sigrity introduces Channel Designer that addresses the challenges associated with the development of high-speed serial links. Channel Designer offers the flexibility and accuracy required to predict bit error rates and ensure reliable operation at speeds that are approaching 10 gigahertz and beyond.  
 
Major Channel Designer Capabilities:
 
·         Unique channel design capture environment including a net-based, block-wise schematic editor for designs ranging from a single net interconnect to an entire bus traversing multiple boards.
·         Highest available simulation accuracy building on Sigrity’s expertise in S-parameter handling for accurate transient simulation for designs from DC to 10 gigahertz and more.
·         Incorporation of industry standard IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver models plus unique capabilities such as cascaded model support to simplify the flow.
·         Quick identification of channel design boundaries with targeted equalization and clock data recovery (CDR) modeling to anticipate end-to-end serial link behavior.
·         Flexible reporting and visualization including 2D and 3D eye diagrams, along with bathtub curves, for accurate bit error rate (BER) prediction.

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