TimingDesigner v9.1 Brings SDC Support

Published: 21 October 2008
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EMA Design Automation introduces TimingDesigner v9.1. The standard tool for interface timing design now has the ability to generate SDC timing constraints from timing diagrams. Users are able to visually define requirements and generate SDC to drive, place and route.
 
The SDC support also adds the ability to interface with FPGA and ASIC design flows. With focus on the Altera FPGA, graphical timing analysis features enable the development of SDC timing constraints for Altera devices. General productivity enhancements and updates are included. 
 
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