FPGA Design Tool Suite Optimizes I/O Placement

Published: 05 May 2008
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According to Lattice Semiconductor Corporation, the tool, ispLEVER® 7.1 includes functional and performance-enhancing features like an FPGA Simultaneous Switching Output (SSO) Analyzer. FPGA designers can analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. The design tool claims to deliver up to 30% faster FPGA design compile times and can support multi-processor powered design compilation to achieve the fastest timing closure. 

A power calculator allows FPGA designers to analyze and optimize power requirements early in the design process. The Lattice Power Calculator includes a user-friendly interface that enables power analysis at the block level and examination of "what-if" scenarios by changing design environment variables. 
 
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