Elgris Releases E-Builder Symbol Builder and FPGA-to-PCB Verification Tool
E-Builder symbol builder and FPGA-to-PCB verification tool is vendor independent.
Allows intelligent symbol building targeted to high pin count devices. Is table-driven and supports templates and multiple vendor styles. Has an extensive set of features for putting pins in groups or sections, and arranging pins by selected criteria. Comes with Symbol Editor that works with two symbols simultaneously, expediting moving pins between them. Generated symbols can be saved to OrCAD, ConceptHDL, Pads, Powerlogic, DxDesigner, Eagle, EDIF and internal binary format. Symbols can also be automatically placed on a page with proper wiring and decoupling capacitors added for FPGAs and similar. Addresses issue on how to match FPGA signals to nets on a PCB board where an FPGA device is placed. Supports all major FPGA device families, FPGA constraints formats and rules-driven comparison wizard. Allows FPGA symbols to be built with pins with signal names that correspond to PCB net names on a board.
