Virtuoso system design platform is a formal, streamlined and automated co-design and verification flow between Virtuoso, Allegro and Sigrity.

Enables concurrent design across chip, package and board. Is said to minimize errors and reduce layout versus schematic (LVS) time between IC and package from days to minutes. Allows IC designers to include system-level layout parasitics in IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. Automatically generates "system-aware" schematics that can be used to create a testbench for final circuit-level simulation.

Cadence Design Systems

cadence.com/go/virtuososdp