Cadence Sigrity 2017 introduces several key features specifically designed to speed PCB power and signal integrity signoff.

New features include Allegro PowerTree topology viewer and editor, which enable quick assessment of power delivery decisions early in the design cycle, and a PCI Express (PCIe) 4.0 compliance kit for checking signal integrity compliance with the latest PCIe specification when it is certified later this year. Compliance kit automatically qualifies signal quality standards instead of manually checking and measuring against standards documents.

PowerTree user interface allows a power topology to be viewed for quick and accurate determination of the best path for power delivery. Allows easy editing as designs change. Information stored in the environment is then used later in the design cycle to provide automated setup of post-route power integrity analysis for faster closure.

PI models can be saved and automatically retrieved from the analysis model manager library when design components are reused. This method also speeds development by automating processes that in the past have been repeatedly carried out manually.

Cadence

www.cadence.com/go/sigrity2017

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