Cadence OrbitIO Interconnect Designer, System-in-Package (SiP) Layout and Physical Verification System (PVS) are now included in an IC packaging design and analysis suite, enabling multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB. For advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs, the new capabilities are said to enable faster multichip integration for smaller, lighter and power-optimized wireless mobile devices. Orbit Interconnect Designer enhancements strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. Enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance.

Cadence Design Systems, cadence.com/news/ICpackaging172