Sigrity 2016 includes automated support for IBIS-AMI model creation, fast and accurate channel model extraction using multiple field solvers, and an automated power-aware signal integrity analysis report to validate a virtual USB 3.1 channel. Leverages validated equalization algorithms and provides automated methodology for combining, paramaterizing and compiling algorithms into an executable model. "Cut and stitch" technology creates accurate channel models faster using a mix of hybrid and 3D full-wave field solvers. With minimal manual intervention, serial link channel can be divided into sections, solved for and automatically stitched together into a single interconnect model. Rapid model extraction technique enables trade-offs of various signal routing and layer transition strategies.

Also includes:

• New quasi-static 3D field solver integrated with 3D full wave and hybrid solver technology available for both IC package and PCB analysis
• Electrical Performance Assessment integrated directly into the IC Package Designer's layout environment
• Optimized decoupling capacitor schemes updated to Allegro® PCB layout
• Improved Power Integrity analysis methodology for PCB designers

Cadence, cadence.com/news/sigrity2016