Applying UHDI only where density and performance demands require it can reduce layer counts, improve yields and lower costs without sacrificing electrical performance.

One of the most common assumptions PCB designers make when investigating ultra HDI (UHDI) technology is that every layer must be built with ultra-fine geometries using semi-additive processing (SAP) or modified semi-additive (mSAP) processing. In practice, most UHDI stackups are a combination of conventional layers and UHDI layers. This approach – call it selective UHDI – places UHDI layers exactly where they deliver the most benefit and lets conventional layers handle the rest, resulting in a mixed-process stackup.

Apply UHDI selectively, not to every layer. Selective UHDI is the practice of applying UHDI fabrication only to the layers that need it, rather than across the entire board. The result is a mixed-process stackup: a PCB architecture that combines UHDI layers, built using semi-additive processing (SAP) or modified semi-additive (mSAP) processing, with conventional subtractive layers in the same board. The mix here is one of fabrication processes, not dielectric materials, which sets it apart from the material hybrid stackup that combines laminates such as Rogers and FR-4.

The distinction between HDI and UHDI is based on the feature thresholds defined by the Naval Sea Systems Command (NAVSEA) Crane. High-density interconnect (HDI) is characterized by BGA pitches of 0.8 to 1mm, trace and space around 75µm (3mils), and microvias of 100µm (4mils) or greater. UHDI extends each of the following: BGA pitches of 0.5mm or less, trace and space of 65µm or less, microvias of 50 to 75µm (2 to 3mils), and impedance control within 3 to 5%.

Do all layers in a UHDI PCB need ultra-fine geometry? No.

Not every layer in a UHDI board requires ultra-fine geometry, and applying it where it isn’t needed adds cost and process complexity without adding design value.

From a fabrication standpoint, UHDI processing carries tighter process windows than conventional subtractive layers. Every layer committed to those tighter windows is a layer where plating distribution, imaging accuracy, seed layer uniformity and registration all need to perform at a higher level. Applying UHDI only where needed improves yield, reduces costs and keeps the fabrication process stable.

Where UHDI layers should be placed in the PCB stackup. BGA breakout zones and dense signal regions need semi-additive geometry for smaller capture pads, tighter via structures and sub-65µm routing. Power planes, ground references and broader signal layers don't. Keeping conventional processing where it belongs leaves those layers stable and predictable. A 0.5mm pitch BGA, for example, may require UHDI routing on the outer build-up layers to escape cleanly, while inner layers handling power distribution remain entirely conventional. However, where VIPPO and copper-filled microvias are required on the outer layer, don’t add the complexity of UHDI there; keep those structures below the outermost layer.

Impedance-sensitive nets in RF and high-speed regions are the other natural fit. The more consistent copper geometry and straighter sidewalls produced by semi-additive processing translate directly into tighter impedance control and more predictable electrical behavior, a benefit that applies even beyond fine-line features.

How should designers plan a selective UHDI stackup? Start early.

Selective UHDI planning works best when it starts early, before routing begins, not after the design is nearly complete.

Identify which areas of the board are actually driving the density or performance challenge. In most designs, that comes down to a specific region: fine-pitch BGA breakout, a dense RF section or a cluster of high-speed nets with tight impedance requirements. Those areas map to specific layers.

The question becomes: which layers can remain conventional without compromising the design intent? In many cases, the answer includes most of the stack. Routing away from dense breakout zones, the power delivery structure, and the reference planes rarely require anything beyond standard subtractive-layer capability.

Figure 1. Selective UHDI applies ultra-fine geometries only where density and performance demands require them, while conventional layers handle power distribution and general routing.

Why should designers involve their fabricator early?

Fabricators who regularly produce mixed-process boards have worked through those variables and know which material combinations behave predictably together, where registration is most sensitive, and how to sequence the build to keep the process stable from start to finish. That accumulated knowledge does not appear on a capability chart, but it directly affects yield.

Early fabricator involvement results in a collaborative effort designed around a real process window. That alignment between design intent and fabrication reality is where yield improves, surprises decrease, and first-article builds run more smoothly.

Early fabricator engagement is also the right time to discuss opportunities for layer count reduction. UHDI's routing efficiency often enables the same electrical design to be achieved with fewer total layers than a conventional HDI approach would require. In a mixed-process build, that reduction can come from the UHDI layers opening routing channels that previously required additional conventional layers to resolve. The effect can be dramatic: escaping a 0.5mm pitch BGA with conventional 75µm routing can demand as many as 12 routing layers, while fine UHDI geometry can resolve the same escape in as few as two, collapsing layers that would otherwise exist only to break out a single dense component. Fewer layers mean fewer lamination cycles, with direct implications for reliability, weight and overall cost.

When selective UHDI make sense. Selective UHDI makes sense when one or more of the following conditions are present:

• BGA pitch is at or below 0.8mm, and escape routing is driving layer count up.
• Line and space requirements below 75µm are confined to specific board regions.
• RF or high-speed nets require tighter impedance control than conventional processing can reliably deliver.
• Miniaturization goals are pushing board size and layer count, but not every layer needs ultra-fine geometry.
• Cost and yield need to be balanced against routing density requirements.

Selective UHDI vs. Full UHDI: Which Do You Need?

The decision comes down to scope: how much of the board actually needs ultra-fine geometry? When only specific regions drive the density or performance challenge – a fine-pitch BGA breakout, a dense RF section or a cluster of high-speed nets – selective UHDI is the right fit: UHDI where it is needed, conventional layers everywhere else. A full UHDI build only makes sense when the entire board genuinely requires sub-65µm features throughout, which, in most designs, is not the case.

Does Selective UHDI Cost Less Than Full UHDI?

In most cases, yes. Every layer committed to UHDI processing carries tighter process windows and lower yield than a conventional subtractive layer, so confining UHDI to the layers that need it, rather than applying it across the whole board, lowers both cost and risk. A mixed-process build keeps the tightly controlled, higher-cost processing on the fine-pitch breakout, dense routing, and impedance-sensitive layers, while conventional layers handle power, ground and general routing at standard cost. The savings come from higher yield on those conventional layers and from the layer-count and lamination-cycle reductions that UHDI routing efficiency makes possible.

The question is never really “should we use UHDI?” The more useful question is “which layers actually need it?” Answer that thoughtfully, build the stackup around it, and the benefits of tighter routing, fewer layers and better electrical control follow naturally. The best designs have always been intentional ones. UHDI just raises the stakes.

Selective UHDI planning. Layer assignment should be driven by where the design challenge actually is, not by applying the smallest possible features everywhere.

UHDI layers belong around fine-pitch BGA breakout zones, dense signal regions and impedance-sensitive RF or high-speed nets. Conventional layers handle power distribution, ground references, and broader routing and perform better when they are not pushed into tighter process windows unnecessarily.

Clear communication in the data package about which layers are UHDI and which are conventional is one of the most avoidable sources of first-article delay. Fabricator involvement before the stackup is locked in is not optional; it is where mixed-process builds either come together cleanly or create problems that are expensive to unwind.

Anaya Vardya is CEO of American Standard Circuits and ASC Sunstone Circuits. ASC works closely with customers and design teams on advanced PCB technologies, including RF, HDI, rigid-flex and UHDI, with a focus on turning complex fabrication realities into practical design guidance.