A summary of how to order layers to achieve target impedance values.

Printed circuit boards are becoming highly dense, hosting all kinds of high-speed interfaces. The bandwidth of the clock frequencies reaches hundreds of GHz, leading to complex issues related to EMI interference, crosstalk, reflections, jitter and losses.

These new challenges impact all processes involved in design, analysis, manufacturing and testing. Manufacturers employ advanced and complex technologies and methods to accommodate the higher density of functionalities packed into smaller components. To manage losses and achieve desired functionality at higher speeds, research into new materials is leading and revolutionizing this industry. The PCB is at the center of issues related to signal integrity, power integrity, electromagnetic interference, crosstalk, mechanical, thermal and more. It also plays an integral role in solutions for each of these challenges.

These issues begin at PCB stack-up design, since a well-designed stack-up forms the foundation of a strong and stable PCB. It acts as the fundamental backbone of the PCB design structure that impacts signal integrity, power distribution and signal impedance. A sound and properly designed stack-up minimizes the circuit’s vulnerability to external noise and helps improve the electromagnetic compatibility of the product (Figure 1).

Figure 1. The PCB is the center of a host of electrical, mechanical and thermal issues.

What follows is a summary of some key SI-related points in simple terms, without delving into deep mathematical calculations and complex theories. The stack-up is the arrangement of conductive and insulating layers within a PCB. The total number of layers in a stack-up is determined by the higher pin count ball grid array (BGA) components, complexity of the circuit, its placement and performance requirements. The order of these layers is very important and should be finalized carefully, taking into consideration manufacturability requirements and signal integrity (Figure 2).

Figure 2. Sample PCB stack-up configuration.

Regarding insulating layers, pay special attention to the properties of the dielectric material and its width. The type of material and its thickness significantly impact signal speed, impedance and losses. These materials play an important role in managing the mechanical and thermal stresses in the PCB, while the width of the dielectric material also contributes to the overall PCB width. Some conductive layers serve as power or ground planes (power/GND), while others function as dedicated signal layers. Designers use plane layers to establish power delivery networks (PDN) and carry high power signals from the power supply to their respective loads. In contrast, signal layers connect all manner of critical high-speed and other general inter-IC connections. Critical signals, which include high-speed signals on a PCB, require special attention and are highlighted in IC vendor datasheets.

Designers cannot route these signals on just any layer; they must meet specific timing and impedance-based requirements for the product to function correctly. For example, consider memory, the bread and butter of every design. DDR3 memory, for instance, operates as a high-speed interface that contains all types of signals, including data, strobes, address, command, control, status and clock signals. This interface can feature over 100 signals, each with specific timing and impedance requirements (Figures 3 and 4). The strobe and clock signals are differential in nature, while the remainder are single-ended, with different impedance requirements.

Figure 3. 50Ω single-ended signal routing in DDR3 interfaces.

Figure 4. 100Ω differential pair routing for DDR3 clock and strobe signals.

Regarding timing-related constraints, at a high level, data bits exist as bytes/lanes and each lane has its own differential strobe. In each lane, every data bit must maintain a timing relationship with its strobe and match the length of the strobes within a certain tolerance as provided in the datasheet. Additionally, all these data lanes must maintain a specific timing among themselves. All strobes in all lanes must maintain their timing with respect to the clock. The clock requires all address/command/control signals to match its length as well (Figure 5).

Figure 5. Serpentine routing for length-matching of DDR3 data, strobe and clock signals.

Design engineers mention these delay requirements in terms of time units, such as picoseconds or nanoseconds, while PCB layout designers prefer length-based constraints such as millimeters or mils. Converting time into distance depends on the signal’s speed on that particular layer, which relies on the properties of the dielectric material around the signal trace. These material properties also impact the trace impedance. All these factors are a part of PCB stack-up design, linking both speed and impedance closely to this design process. Let's explore how this connection works.

Stack-up design → Signal speeds

When electrical signals travel on the PCB traces, they generate waves of electromagnetic fields around them that travel along with the signals. These electromagnetic (EM) waves travel through the materials surrounding the PCB trace. In free space, EM waves propagate at the speed of light, which is 3x10^8m/s. In a PCB, however, there is no free space; instead, dielectric materials surround the signal traces. The speed of the EM fields in a PCB is affected by the effective relative permittivity (Er) value of the insulating material and is therefore equal to the speed of light in a vacuum, divided by the square root of the effective Er value of the insulating materials surrounding the transmission line; i.e.,

v = c / sqrt(Er)

In PCBs, FR-4 is the common dielectric material used, and its dielectric constant has a range of values from 3.9 to 4.7. To make it simple, take Er = 4 and put it in the above equation, which then reduces to

v = c / sqrt (4) = c / 2 = 1.5 x 10^8m/s = 150mm/ns ~ 6in/ns

In a PCB, the signal trace exists on an external layer (TOP/BOTTOM) or on an internal layer. When the signal trace resides on an internal layer, with a reference plane above and below it, as shown in Figure 6, the configuration is called a stripline configuration.

Figure 6. Offset stripline 1B1A configuration with signal trace between two reference planes.

In this configuration, the trace is completely surrounded by the dielectric material. Thus, the effective dielectric constant for this trace is equal to the Er value of the insulating material. For an Er value of 4, the speed of the signal on the internal layer will be approximately 6in/ns. The configuration in which a Cu trace is present on an external layer with a reference plane under it is called microstrip line configuration (Figure 7). In this configuration, the trace has dielectric material below it while air and solder mask typically sit above it. The Er value of the air/solder mask is less than that of FR-4. As a result, the effective Er value for the microstrip line drops below 4, leadings to higher signal speeds on external layers, meaning v > 6 in/ns. Signals always travel faster on external layers. Therefore, a signal routed on an external layer with a certain length experiences less delay compared to the same length of signal routed on the internal layer. Traces of the same length routed on different layers may have different delay times depending on the effective Er value for each respective layer.

Figure 7. Surface microstrip 1B configuration with a copper trace on the external layer.

From the SI timing point of view, this point is crucial when routing signals in an interface that needs to be length-matched. Route signals belonging to the same group on the same layer to control and easily match the delays. This practice explains why all signals of a DDR3 byte lane are routed on the same layer: it ensures they all maintain the same speed and, consequently, the same delay. Modern day layout tools have this capability built in. If the PCB stack-up is defined properly and all details of material properties and their widths provided, the tool calculates the signal speeds on every layer and can convert the delays into lengths (Figure 8).

Figure 8. Routing byte lane signals on the same layer.

Stack-up design → Trace impedance, Zo

Now it is time to discuss the relation of characteristic impedance, Zo, with the stack-up design. Closely review the Cu trace in the PCB: it makes a parallel plate capacitor with the reference plane below (Figures 9 and 10).

Figure 9. Copper trace and reference plane form a parallel plate capacitor.

Figure 10. Surface microstrip configuration (1B) affects impedance and signal integrity.

In a parallel plate capacitor, the two plates are separated from one another by air or by a dielectric material in the same way the trace is separated from the plane by an insulating material.

The capacitance of the capacitor is linked to the overlapping area of the plates (A), the distance between the two plates (d) and dielectric constant (Er) of the insulating material between the plates, through this formula

Capacitance = (A x Er) / d

For the capacitance of the PCB trace, the above formula can be written as

C = (w x Er) / h

The trace impedance, Zo, and its capacitance are related by the formula

Zo = sqrt (L/C)

It is evident and can be easily concluded that the trace impedance, Zo, is inversely related to its capacitance, C; i.e.,

Zo ⇐ ⇒ 1/C

This means that the factors that will increase the trace capacitance will in turn decrease its impedance, and vice versa. Keeping in view the formula C = (w x Er)/h, it can be concluded that:

• Increasing trace width, w, will increase trace capacitance but will decrease the trace impedance, Zo, and vice versa.
• Using insulating material with higher dielectric constant value (Er) will increase the trace capacitance, but will decrease its Zo and vice versa.
• Increasing dielectric material thickness (h) will decrease the trace capacitance, but will increase its impedance, Zo, and vice versa.

So, in a nutshell:

The trace impedance inversely relates to its width (w) and the dielectric constant value (Er) of the dielectric material, while it directly relates to the thickness of the dielectric material. These factors directly connect to the PCB stack-up. These parameters are tweaked to find suitable trace widths that achieve different target impedance values for all SE and diff-pairs. While making these calculations, ensure that the specified trace widths and spacing values are manufacturable and that selected materials are economical. Additionally, ensure impedance targets are met while keeping the thickness of the dielectric materials so that the overall PCB thickness is within allowable specs.

The stack-up design directly impacts signal speeds and trace impedances through the selected material properties in PCB layer construction. Engineers calculate and control parameters that affect multiple things at once. For example, changing the value of Er impacts both the trace impedance Zo and the signal speed. Sometimes, engineers alter material properties simply to achieve target impedance values, ignoring their impact on signal speeds. The result can be timing issues – product failure.

Akber Roy is chief executive of Rush PCB (rushpcb.com), a printed circuit design, fabrication and assembly company; This email address is being protected from spambots. You need JavaScript enabled to view it..