Fabrication-aware simulations to aid PCB design success.

As engineers design printed circuit boards (PCBs) to operate at higher data rates, the system’s signal integrity becomes increasingly sensitive to the variation in the fabrication process. A practical design is a software-defined design that includes realistic fabrication variation.

Typically, the PCB material properties in electronic design automation (EDA) software have default values. These ideal values for the material properties and PCB cross-sectional geometry are often called the as-designed values. On the other hand, after fabrication, the as-fabricated properties are the measurable numbers and dimensions from a physical board.

Although these ideal, as-designed values provide adequate performance prediction, it is increasingly important to include as-fabricated values for material properties and cross-sectional dimensions in the simulation to achieve first-pass product success and reduce the number of board spins.

This article focuses on the impact of etchback and dielectric loss tangent. It discusses their impact on signal integrity, how to better characterize them and how to include them in a practical design to better predict performance.

Impact of Etchback

The as-designed, ideal trace cross-section is a perfect rectangle. In reality, however, a fabricated trace cross-section often resembles a trapezoid (Figure 1).

Figure 1. At left, the as-designed, ideal trace cross-section is a perfect rectangle. At right, a fabricated trace cross-section often resembles a trapezoid because of the subtractive etching process in the PCB process. (Source: eurocircuits.com/quality/microsections/)

The characteristic impedance of a cross-section is proportional to the resistance per unit length (PUL) and the structure’s inductance per unit length (PUL). When the etchback decreases the cross-section area, both the resistance PUL and inductance PUL increase.

As a result, this trace etchback increases trace impedance so that the as-fabricated impedance is higher than the as-designed impedance. The narrower the starting trace width, the more impact the trace etchback has on the as-fabricated impedance.

By including the etchback in the simulation phase of each design iteration, engineers can design boards that are less susceptible to fabrication variation.

Impact of Loss Tangent

The loss tangent has many names in the industry. Some call it tanD (tan-dee), some call it Df (dee-eff), which means dissipation factor, and others tan-delta. Regardless of the name, it informs a designer how much electrical energy is dissipated and not transmitted in a dielectric material. With a larger Df number, more electrical energy is dissipated.

A typical FR-4 material has a Dk (dielectric constant) of 4.4 and Df around 0.02. A high-speed material from Isola I recently came across has a Dk of 3.1 and Df at 0.0015.

The description of the Isola material states, “[this material] has been engineered for very high data rates of >100Gb/s [...].”¹

Let’s examine how the low Df impacts the highest operating data rate.

From Dr. Eric Bogatin’s Rule of Thumb, the maximum attenuation (insertion loss) at the Nyquist for an acceptable eye-opening is about -10dB without equalization.²

Let’s assume we have a 5" trace made from a perfect conductor, so only the dielectric contributes to the insertion loss (IL). We can extend the dielectric loss relationship to approximate how high of a data rate we can run on the low-loss material.³ The approximation is shown in Figure 2, where data rate is in Gbps, IL is insertion loss in dB, Df is dissipation factor, Dk is dielectric constant, and len is the trace length in inches.

Figure 2. A formula to approximate data rate limits on a low-loss material.

Assuming the acceptable attenuation is 10dB, for FR-4, where the Dk = 4.4, Df = 0.02, and considering only dielectric loss, the highest data rate is 47.7Gbps.

For the low-loss material where the Dk = 3.1 and Df = 0.0015 and considering only dielectric loss, the highest data rate is 757.3Gbps.

Considering the dielectric loss alone, our estimation confirms Isola’s claim that the operational data rate is greater than 100Gbps.

By finding the correct value loss tangent, engineers can better predict the channel’s performance and know when the design has met the requirements.

Characterizing Etchback and Loss Tangent

Etchback. The most straightforward way of looking at etchback is through a cross-section analysis. PCB cross-section analysis is a destructive process that involves cutting a small section of the PCB to examine its internal structure and quality. With the help of my advisors, I have developed a nondestructive technique to get an effective etchback, which was detailed in my dissertation.⁴

Loss tangent. In the high-speed industry, the clad dielectric measurements are the most common, where metal conductive layers sandwich the dielectric material. This method provides a more realistic representation of the dielectric properties of the actual PCB, considering the presence of the copper layers and their impact on the overall performance.⁵

Intel’s Delta-L technique is a good example of a clad measurement.⁶ It provides transmission lines of different lengths as test coupons to extract the insertion-loss-per-inch measurement.

Then, the measurement-based model is usually used to extract the dielectric loss tangent from the results. A loss tangent extraction process might look like this:

1. Measure the S-parameters of Delta-L structures
2. Use the Delta-L utility in Physical Layer Test System (PLTS) to find the insertion-loss-per-inch at 1GHz
3. Create a 1" transmission line model with known geometry dimensions and material properties in Advanced Design System (ADS)
4. Vary the loss tangent value in ADS until the insertion loss at 1GHz matches with the value from step 2
5. Report the final loss tangent value as the as-fabricated loss tangent.

How to Create a Practical Design

To create a practical design that accounts for realistic fabrication variation, engineers must integrate the etchback and loss tangent characterization into the design and analysis process. Here are key steps to achieve this:

1. Characterizing the etchback
2. Characterizing the as-fabricated loss tangent
3. Inputting these parameters into PCB design and analysis software.

To quickly include the as-fabricated loss tangent and etchback in a board-level simulation, consider appropriate signal integrity analysis software. Such tools can quickly take in PCB board layouts and provide S-parameters, eye diagrams, TDR and simulation reports, and detect return plane discontinuities.

Conclusion

Integrating as-fabricated material properties like etchback and loss tangent into PCB design and analysis is essential for ensuring signal integrity and fabrication success, particularly in high-speed applications. Engineers can create practical PCB designs that meet performance requirements and are less susceptible to fabrication variation by characterizing these parameters and incorporating them into the design process.

References

1. Isola, “TerraGreen 400G2 Laminate and Prepreg,” isola-group.com/pcb-laminates-prepreg/terragreensup-sup-400g2/.
2. E. Bogatin, “How Much Attenuation is Too Much? Rule of Thumb #10,” EDN, 2011, edn.com/how-much-attenuation-is-too-much-rule-of-thumb-10/.
3. E. Bogatin, Signal and Power Integrity – Simplified (Signal Integrity Library), 2nd ed. Prentice Hall, page 383, 2017.
4. T. Wang-Lee, “Test Structures and Economical Non-Destructive Measurement Techniques for Multilayer Printed Circuit Board Impedance Characterization,” ProQuest Dissertations and Theses, 2020, proquest.com/dissertations-theses/test-structures-economical-non-destructive/docview/2474825547/se-2.
5. James Baker-Jarvis, et al., “Dielectric and Conductor-Loss Characterization and Measurements on Electronic Packaging Materials,” Tech. Rep., 2020. https://nvlpubs.nist.gov/nistpubs/Legacy/TN/nbstechnicalnote1520.pdf.
6. Intel, “Electrical Characterization Design Methodology,” intel.com/content/dam/www/public/us/en/documents/guides/electrical-character-design-meth-guide-337658-rev001.pdf.

Chun-Ting “Tim” Wang Lee, Ph.D., is an SI application scientist at Keysight Technologies (keysight.com); This email address is being protected from spambots. You need JavaScript enabled to view it..