Assessing the cost vs. performance tradeoff.

In the evolution of silicon implementation, creative solutions to costly problems have become standard practice. One of these solutions is the use of a “chiplet.” A chiplet is precisely what it sounds like: a smaller version of a chip. This doesn’t mean it’s a miniature version. It means that only critical functions that derive significant benefits from a 5 or 7nm fabrication process are included on the chip. Other functions that will work well with 10nm or greater can then be fabricated with appropriate cost savings.

Chiplet technology creates a challenge, however. If all functions were included in the chip, the interfaces could more easily be measured and evaluated. These items now must be accounted for on a package or, more accurately, a system-in-package (SiP) (FIGURE 1). This places greater importance on the electrical characteristics of those interfaces and how that SiP implementation affects that behavior. Thus, there is a need to rapidly assess these issues with minimal effort for maximum results via virtual prototyping.

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