A structured design review process ensures alignment across teams.

One thing is certain about printed circuit board design: change is inevitable. The vernacular surrounding the art and science of PCB design gives credence to this statement. Upfront, it’s a schematic editor that leads to a layout editor. If you get far enough downstream, you’re working with a Gerber editor. Across the board, the notion of making changes is distilled into the process.

Figure 1. Colorizing power and ground domains helps floorplan the design. The passive components arrayed across the top of the board are mostly bypass capacitors intended for the secondary side. The components below are pre-placed to provide greater visibility into the extent of these subcircuits. (Credit: Author)

Another axiom in effect is: “If it works, don’t break it.” This sentiment is especially strong where a circuit must be qualified through a regulatory body. If a radio meets the requirements, it’s as if it were written in stone rather than copper. Change is for the better unless it adds unreasonable risk or lengthens the schedule.

It’s important to maintain that continuity while making improvements as needed. A second pair of eyes is always helpful and, in fact, the more the merrier, up to a point. The mechanical engineering of PCB layout is the foundation of the circuit board, while embedded electronics are the vessel for the software. Testing the circuit lies somewhere between these two camps. Herding all these cats requires finesse from the PCB designer.

Figure 2. Capacitors on the bottom (red) respond to a 1.2V patch of pins (magenta) in the middle of the processor. Surrounding them is a ring of 2.5V (yellow). Finally, the outer voltage domain is for 1.8V (cyan) with a side of 3.3V (green). Completing this PDN is a top priority. (Credit: Author)

Getting the lay of the land. Kicking off a layout usually starts with the mechanical information. Design reuse of the mechanicals is a common theme. The trick is that later upgrades rarely come in the form of a reduction to the bill of materials. We fix electrical problems with more electronics, perhaps a new filter or a shield. Sometimes, it’s another mounting hole, and it could be all those things at once.

We compete in the market with new features to enhance the product. Even with the same feature set, we’re compelled toward faster, smaller and more efficient designs. You could say that revision 1 is just messing around, while revision 2 is after you find out what was overlooked in the rush to market.

With all of this going on, we can’t go it alone. Tight schedules push us into a corner. Backtracking is a waste of that precious time and money. The goal is always to do it right the first time. All this is just to say that we need clear communication on every aspect of ongoing improvements.

Arbitrary and capricious “changes” can backfire. Don’t go at it alone. Schedule a design review at each stage of the design cycle. Day one of the schedule is a good time for setting milestones. Once you have an outline and a stackup, you have enough data for a budgetary quote from your vendor(s). “Vendor” should always be plural for the bare board as well as the components.

Figure 3. Fan-out optimized for bypass cap placement and avoiding choke points in the power planes. (Credit: Author)

Being prepared to kick off placement. The mechanical outline and stackup should account for all packages involved, as well as the routing and placement keep-out regions. If you don’t want routing below a component type, the footprint should include a route keep-out. I built a route keep-out into every inductor since no one wants routing under there. Some sensors require more clearance than a standard part. That extra space should be incorporated into the virtual part.

Figure 4. When all was said and done, the board grew horizontally while the technology moved from plated-through-hole to HDI in order to place the DDR memory belly-to-belly. (Credit: Author)

The more absolute rules you can encapsulate, the better. This serves two purposes. It reduces your workload and shows reviewers that you’re aware of the constraint and have acted. Keep-ins, keep-outs, headroom limits and other restrictions can be a hassle, but the payoff is a compliant PCBA that fits where it belongs and works as intended.

The design review. Design reviews will be boring for someone with no stake in that part of the process, so the attendee list should reflect that. The mechanical engineer is required to verify that the board outline and all non-electrical features were imported correctly. That’s square one. There’s no point in inviting the test engineer to that review. Loop them in when you’re fairly certain that the test points have optimal coverage. By that point, the ME is out of the picture. Their return could be disruptive.

Certain milestones deserve a design review.

1. Mechanical outline review, including all components, holes and other features covered by the outline drawing. An outline drawing might not yet be available. At a minimum, we compare the layout to the 3-D model to see if everything makes sense. This should involve you and mechanical engineering. After this review, it makes sense to spool up the fabricator so they can provide trace geometry and any other input related to the proposed stackup.
2. Library completion with all components randomly placed outside the board outline. This is you, the EE and maybe copy the project manager. If you’re lucky enough to have a dedicated librarian, loop them in.
3. Critical placement with RF chains routed and major ICs in their proposed locations. You, the EE and signal integrity, and at least one of your peers, if possible.
4. Detailed but rough placement with your best effort at fleshing out the power delivery network (PDN). This is a good time to organize your reference designators for the first time. Doing so will make the final push a little more bearable. You, the EE and power integrity.
5. After fanout of the most complex integrated circuits. You the EE and, again, copy the project manager. The assembly team, whether in-house or contracted, should be included for a placement evaluation. They can advise you on the assembly subpanel and any test coupons, as required. Markup every document shared as Preliminary!
6. When memory or other high-speed signals have been connected and length-matched as required. Bring back signal integrity and call on test engineering. The EE should be in the loop daily at this point anyway.
7. Routing of the miscellaneous unnamed traces. You, the EE, your manager and a friend to balance out the power dynamic. After this, your main objective is punching in gratuitous vias for thermal and signal integrity compliance.
8. Full documentation package with all design rule errors squared away. Make a print of every layer and each drawing so there’s something to mark up. Invite mechanical engineering, electrical engineering, project management, your manager and the SI/PI team. CC everyone else who contributed to the design effort.

Depending on the design’s complexity and nature, some of these may be combined, but it still pays to break the job down into milestones so you can tell whether the project is on track to meet the tape-out date. Waiting until tape-out day to say that the board isn’t done could be seen as a failure on your part, particularly if you’ve been on “radio silence.” Keeping on top of the schedule is a part of managing expectations.

Figure 5. A sanity check after moving the JTAG connector. I will also revisit the inductor between the SMB connectors in the upper corner. (Credit: Author)

The number of touchpoints will vary with each design. Some folks will need a special reminder to make it to the meeting. I remember a signal integrity guy hiding from everyone while using the design review to catch up on his emails. It cuts both ways. Modern times have spread out the workforce, so there are likely to be people phoning it in. Make sure they have a chance to speak and that no one in the room talks over them.

Schedule design reviews as soon as practical. Everyone’s calendar fills up by the time they get to work that day. Scheduling these reviews at the start of the layout gives you flexibility to include the people you need, when you need them. This can be done while the schematic is in progress, with the schematic-complete milestone penciled in somewhere along the way. Let’s be honest here. The schematic will not be done on the day you start the layout.

When things outside of your control happen, it’s the only time you can be forgiven for proposing a whole new set of dates for the follow-on milestones. Product managers are under pressure too. They do not want you to pad the schedule for unforeseen circumstances. We act like everything will fall into place at the right moment, but it doesn’t happen often.

Hope for the best while preparing for the inevitable. While Sun Tzu often gets credit for it, Helmuth von Moltke said, “No plan survives contact with the enemy.” To be clear, your coworkers are not the enemy, but they do tend to disrupt the best laid plans. As we work with those around us, we learn who is most likely to surface with a last-minute request.

We manage those people the same way we manage an overwhelming concentration of “rats” coming out of an SoC. Ping them early and often. Ask how confident they are in the input provided at any stage. Some people will hold back on giving new information until they are certain that it is the best way forward. They keep their cards close to the vest until they are compelled to share. At the same time, the vendor can’t answer questions that weren’t asked.

I remember at Qualcomm when we onboarded an engineer on a work visa. She was from Australia and informed us that she received the very last visa issued for that year. I remarked that she was going to fit right in and added that, “If it wasn’t for the last minute, nothing would get done around here.” It isn’t just Qualcomm. It’s human nature. It’s incumbent upon us to herd those cats to get the job done by the 11th hour, when it all comes together.

John Burkhert, Jr. is a principle PCB designer in retirement. For the past several years, he has been sharing what he has learned for the sake of helping fresh and ambitious PCB designers. The knowledge is passed along through stories and lessons learned from three decades of design, including the most basic one-layer board up to the high-reliability rigid-flex HDI designs for aerospace and military applications. His well-earned free time is spent on a bike, or with a mic doing a karaoke jam.