How fully has AI taken over packaging, power and manufacturing priorities?

With more than 92,000 visitors and 1,850 exhibitors, Nepcon Japan celebrated its 40th anniversary in Tokyo in late January. Exhibit areas included IC and sensor packaging, power devices and modules, test, electronic component and materials, fine process technology and printed wiring boards, plus halls devoted to automotive, smart factory and robotics.

Almost every booth in the smart factory section mentioned AI. Automotive components and analysis services were on display. In Automotive World, MarkLines displayed its teardown of BYD’s new, higher-priced (¥23 million or $146,818) SUV. The teardown focused on the frame, battery and electronic boards and included a BoM analysis. LTEC featured automotive boards the company examined for its IP analysis. Inventec, known for its PC and server design and manufacturing, provided details of its expansion into automotive electronics with IATF 16949-certified facilities in Taiwan, China, the Czech Republic, Mexico and Thailand. Solutions focused on vehicle computing, e-cockpit domain controller/cluster, connectivity and smart mobility (digital key/wireless charger) with hardware and software integrated solutions. The robotics section included Sony’s OmniBall, a wheel used for robotics that can move on a step with a height close to the diameter of a ball.

Crowds overflowed the special conference sessions on advanced packaging focused on high-performance packaging trends driven by the AI data center demand. Resonac provided an update on consortia activities. The Kawasaki Packaging Solution Center’s research focused on 300mm wafer and 510mm x 515mm panel development for silicon and organic interposers with technology developments in fine bump interconnection (10µm), fine circuitry (1µm lines/spaces) for interposers and large package (140mm x 140mm substrate) reliability. The new advanced panel-level interposer center development activities will cover production developments for large interposers (8x to 12x reticle size) on panels. At least 27 companies are participating in this research at the Ibaraki site. The new packaging and power solution center in Oyama will focus on power module development, including power device performance, materials and thermal management.

The TSMC Japan 3DIC R&D Center’s presentation focused on the challenges of AI compute packaging and described the rapid evolution of chip-on-wafer-on-substrate (CoWoS) interposer technology at TSMC. While Si interposer (CoWoS-S) has been in production for more than a dozen years, redistribution layer interposers (CoWoS-R) and CoWoS-L, which include a silicon bridge for higher density, are moving into production to handle the demand for larger interposers. TSMC indicated that by next year, a 9.5 reticle-size CoWoS-L will be ready to support hybrid bonded solutions and high-bandwidth memory (HBM) integration. TSMC described the drive to panel-level production of RDL interposers to support the increased number of HBM stacks. TSMC introduced its Compact Universal Photonic Engine (COUPE) stacking process using hybrid bonding for the photonic and electronic chips. The solution is expected to be in production in 2027 for copackaged optics networking applications. Packaging challenges including substrate warpage control, thermal management, new materials needs and test issues were highlighted.

Intel described some of the latest glass-core substrate developments and indicated that an electrically functional test vehicle with three buildup layers on each side of a glass core was demonstrated with a 75µm through-glass via (TGV). A 78mm x 75mm package with an 800µm glass core substrate and 10 buildup layers on each side has been fabricated and singulated without cracking. Assembly and board-level reliability tests are underway.

Another IFS presentation emphasized the company’s embedded multi-die interconnect (EMIB) technology that first shipped in 2017 and is being expanding to finer pitch using a bridge with through-silicon vias (TSVs). The FOVEROS R (RDL) and B (Bridge) technology offerings were mentioned. FOVEROS direct stacking options with microbumps and hybrid bonding (<10µm pad pitch between die) were also described.

Copackaging Advancements

Samsung introduced technology to support advanced packaging, including a 120mm x 120mm substrate with 11 build-up layers on an eight-layer core with options for Si capacitors and MLCC capacitors. The substrate can support copackaging of memory, logic and optics. Trends toward fine features (5µm ~2µm L/S) with 10µm diameter vias, die-to-die interconnects and/or direct RDL on build-up substrates to support HBM that provide signal and power integrity were discussed. Samsung also described R&D on glass core substrates and plans to establish a prototype line.

Rapidus, Japan’s new foundry startup, highlighted described its panel-level package developments focused on a 600mm x 600mm panel with 2µm line and space capability. The line is expected to be ready in 2028.

3D SiP Addresses Power Challenges

Data center power delivery challenges were also highlighted at the conference. The emerging trend toward 800V DC in new data center architectures is driving demand for advances in power delivery. As racks reach up to 500kW, high-voltage direct-to-rack, or near-rack architectures, are driving changes to provide the required power density. ASE and others have noted the high-end computing power supply migration from 12V and single-stage power converter to 48V input, multi-stage power converter with the introduction of integrated voltage regulators, and the addition of L/C to the chip and package. ASE is proposing its 3D SiP technology and embedded technology for reduced X-Y area, reduced Z height, higher component density, shorter electrical and thermal transmission path, and lower power consumption. Vertical power delivery technology, in which the power modules are positioned directly beneath the processor to reduce the distance current must flow through the substrate, can significantly decrease power delivery network losses. Suppressing power noise is also critical. ASE notes that vertical power delivery provides an 8% power savings and a 30% size reduction compared to lateral power delivery.

Providing efficient power delivery to high-performance devices such as AI training and inferencing ICs is driving the development of new high-performance capacitors and even the adoption of embedded capacitors and voltage regulators in package substrates. Exhibitor Saras Micro Devices highlighted its high-density capacitor and integrated voltage regulator technology that can be embedded in the substrate.

Power modules were a major focus of the show, with hundreds of exhibitors and numerous presentations. Infineon described its power module options, highlighting its module developments to support higher voltages. As data centers move to higher voltage, the importance of this segment of the industry will grow, and Nepcon will be an important show to attend to follow this trend and other key developments.

E. Jan Vardaman is president of TechSearch International (techsearchinc.com) and a contributing editor for PCD&F/CIRCUITS ASSEMBLY; This email address is being protected from spambots. You need JavaScript enabled to view it..