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FEATURES

SIGNAL INTEGRITY
Generalized I/O Timing Analysis, Part 2
Timing analysis is a complex engineering process. It requires the engineer to deal with logic design, signal integrity simulations, PCB and chip design timing parameters, and generate length/delay constraints for chip/package/PCB designs. This, the second of a two-part series, looks at how timing and PCB trace lengths affect different real systems, and design tricks for tuning timing.
by Istvan Nagy

PCB WEST RECAP
Hot in the Valley
Something isn’t getting through, as signal integrity classes were packed even though most designers say they don’t perform the critical analysis. 
by Mike Buetow

COVER STORY
PCB Thermal Design Developments
Heat coupling increases as components and PCBs become smaller and more powerful. Designers must take remedial action to bring all components within their respective thermal specifications, but this step is becoming more challenging and constrained, even when preventative measures are taken early in the design process. New 3D thermal quantities can help address thermal problems as they arise. 
by Byron Blackmore, John Parry and Robin Bornoff

FIRST PERSON

• Caveat Lector
  Tough choices call for single voice.
  Mike Buetow
  
  

MONEY MATTERS

• ROI
  Our new stability.
  Peter Bigelow

TECH TALK

• On the Forefront
  Flex’s new twists.
  E. Jan Vardaman
  

• Signal Doctor
  Measuring differential pair loss.
  Dr. Eric Bogatin
  
  
• Designer’s Notebook
  Landing spots.
  Tom Hausherr

• Technical Abstracts
  In case you missed it.