Without a rule of thumb for determining which designs will be enhanced by the addition of buried capacitance, each must be individually evaluated to establish the merits.

Presently, there are several techniques for forming a buried capacitor in the core of a multilayer board. For purposes of this discussion, attention will be directed toward a sheet capacitor, though most of what is presented below can be extended to the other techniques as well.
A buried sheet capacitor is essentially a thin innerlayer. The core is composed of an organic material often reinforced with a woven glass structure; a classic example is FR-4. The copper weight is normally one ounce, and the thickness of the dielectric is typically two mils or less. The innerlayer is biased top to bottom, creating a large capacitor in the interior of the multilayer board. Except for through-hole connecting pads and antipads, the innerlayer is normally not imaged. A cross section is shown in FIGURE 1.

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The purposes of this technology are to offer the designer a technique for EMI suppression and an alternative to the by-pass capacitors normally mounted on the surface of the board to minimize “voltage sag” in the power being supplied to the active devices. A more complete discussion of the electrical performance will follow later.

Material Description

The parameter of primary interest in this construction is the capacitance per unit area of material. Typical values of unit capacitance and other parameters are shown in TABLE 1.

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Potential Advantages and Limitations to the OEM

There are potentially two major incentives for using a buried capacitance PCB design. The first is a reduction in EMI radiation. Buried capacitor innerlayers will reduce EMI radiation and often offer a simple solution for what can be a difficult and time-consuming issue.

The second advantage is a reduction in the number of by-pass capacitors required by a design to overcome “droop” in the power delivered to an active device. Reducing the number of by-pass capacitors obviously results in additional routing space on the outer layers of the board. This can result in a reduction of board size or even innerlayer count, both of which lower the cost of the board. Other advantages are a reduction in assembly cost and a decrease in the number of components, not to mention fewer solder joints that result in improved reliability.

The issues associated with buried capacitance are design tools, board material cost and fabrication. Also, the number of potential fabricators is limited, and the OEM should perform some due diligence to be certain any patent issues are resolved. The designer should also carry out “sanity checks” to verify the buried capacitance design will deliver the charge required to power the devices and the design is compatible with the frequencies associated with the board. A few simple calculations will normally uncover any potential issues of this nature.

EMI Radiation

As frequencies increase, EMI radiation becomes a serious problem. The amount of EMI radiation allowed by the different regulatory bodies is becoming more difficult for OEMs to satisfy, so occasionally, some have elected to use very expensive solutions to resolve this issue. Possibly the most extreme is to coat the entire rack that houses the electronic equipment with a material that will reduce the escaping radiation to an acceptable level. While this approach will overwhelm the issue, it will also drive the system cost to levels that are likely to be unmanageable.

Other OEMs have taken a less expensive approach that, in many cases, resolves the issue but requires some upfront engineering analysis. In particular, only a few boards in the system emit radiation. These can normally be identified by the speed of the board, and processor boards are especially suspected. A procedure, which normally identifies the offending boards, is as follows:

• Measure the EMI radiation from each of the suspected candidates; most likely, this will identify the culprit.
• If this is the case, modify the design of these boards to include top and bottom buried capacitance innerlayers.
• Measure the EMI radiation from these modified designs.
• If the radiation has been reduced to an acceptable level, perform the system test for EMI
• acceptance.
• This is a simple and cost-effective procedure that is consistent with time-to-market considerations.

Replacement of By-pass Capacitors

A popular solution to the so-called “power sag”¹ caused by the high inductance associated with most power distribution designs is the by-pass capacitor. This issue is aggravated as the board’s frequency is increased. Unfortunately, to combat this issue using by-pass capacitors requires an array approach. This is particularly true on high frequency boards. In the array approach, many capacitors are connected parallel with the power and the ground connections of the device. While this is normally very effective, it requires a large amount of area on the outer layers, which in turn, impacts routability. To compensate for this drawback, the use of additional layers and increased board area is required – impacting system cost.

A potential solution to this issue is buried capacitance. In many cases, where buried capacitance has been effectively used, the result has been reduced layer count and board size. Consequently, an appreciable cost savings has been realized.

Another advantage for the OEM is reduced assembly cost. Since board mounted by-pass capacitors are no longer needed, the assembly cost is reduced. That is, the component cost and the labor required for assembly are diminished, not to mention the immediate yield improvement.

Design Issues

The paramount issue inhibiting the use of buried capacitance is a design procedure that will also predict, at the outset, the potential cost benefits of the technology. A proposed methodology is discussed below.

The concerns that should be resolved at the outset are frequency issues and the available charge compatibility between the device and the buried capacitor. This is in the nature of a sanity check to verify there are no first-order issues that will prohibit the use of buried capacitance. The bandwidth limitations and the amount of charge that can be delivered to an active device of a particular embedded capacitance design can be estimated by using the procedures for sizing array capacitors.¹ Additional information can be found in the literature ^2,3 to assist in the required calculations for a buried capacitor design. If these considerations do not present any limitations, then the next step is to estimate the cost savings that can be realized by an embedded capacitance design.

For example, one of the issues in a buried capacitance design is the current limiting effect of vias, primarily caused by the inductance of the via. One of the major results is shown in FIGURE 2. In this analysis, the time to discharge a buried capacitor innerlayer through a 13-mil through-hole via and a 5-mil blind via is calculated for a particular board design.

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One can also use analogs¹ for calculating the time available for the discharge to take place, based upon the speed of the device. Taken together, a designer can perform a first-order analysis to determine the suitability of a buried capacitance structure for a particular design. This and other considerations will determine if the proposed buried capacitor design is technically feasible.

Presuming the design is technically feasible, a cost savings analysis should then follow.⁴ There are also some user groups with software that reportedly performs the same calculations. The analysis is as follows:

Calculate the area occupied by the by-pass capacitors.

• Estimate the additional routing that can be placed on the outer layer in the space originally occupied by the by-pass capacitors.
• Determine the potential cost savings that can be realized by reducing the board’s form factor and layer count.
• Determine, probably from a fabricator, a budgetary estimate for the additional cost of buried capacitance layers.
• At this point, a judgment can be made on the potential cost savings that can be realized by incorporating embedded capacitance into the design. This should include reduction in board cost, assembly cost, cost of removed components and the additional cost of buried capacitance innerlayers.
• This judgment should be quantified by an estimate of the confidence in the potential savings, vis-á-vis the amount of savings. 
• If the amount of savings justifies the cost of a redesign using embedded capacitance, then the redesign should be attempted.
  

Admittedly, judgment and some risk are involved in the process, which is the case in nearly all management decisions. According to numerous antidotal reports, however, the cost savings can be huge.

There is a time-to-market component here as well. In a conventional design, it is often necessary to go through several design iterations of a part number until the power sag is overwhelmed. Each redesign normally requires new model boards (at a quick turn price) and a bench test; all of which are expensive and increases the time to market. Very often, this redesign impediment can be largely avoided by incorporating an embedded sheet capacitor package. This streamlines the product introduction process from conceptual design to market, thereby undercutting the competition.

As with most engineering issues, there is not a procedure to absolutely determine if a buried capacitor approach is best for a particular application. Choosing a buried capacitance approach will always involve some risk. An overview which may be of help understanding the risk to potential reward ratio for this technology is contained in the IPC white paper.⁵

At this point in the evolution of the buried capacitance technology, there isn’t a rule of thumb for deciding if a board design will be enhanced by the inclusion of buried capacitance innerlayers. The merits of each design should be evaluated on a case-by-case basis. PCD&F

References

1. Johnson and Graham, High-Speed Digital Design, Prentice Hall PTR.
2. Parker, J. Lee, “Buried Capacity Analysis,” Printed Circuit Design & Manufacture, June 2006.
3. Bergstresser,T. et al, “Embedded Capacitance Materials and Their Applications in High Speed Designs,” IPC Expo 2003.
4. Devenish and Palczewski (Harris Corporation), The Embedded Passives Journey, IPC APEX, 2007.
5. John Andresakis, David P. Burgess, Dennis Fritz, J. Lee Parker, Richard Snogren and Valerie A. St.Cyr; “Embedded Passives: An Overview of Implementation, Benefits and Costs.” IPC – Association Connecting Electronics Industries White Paper, March 2, 2009.

J. Lee Parker is president of JLP Consultants and can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..

Ed note: This article was presented at the IPC APEX Expo 2009 Technical Conference.