Thermal modeling balances the tradeoffs between thermal compliance and signal integrity requirements.

Attempting to satisfy an increasing number of PCB design constraints is putting more pressure than ever on designers. The risk of failure of either functional performance or reliability increases with each new generation of design. One of the fastest emerging design tradeoffs is between thermal compliance and signal integrity. High clock speed, coupled components need to be close together to ensure no signal degradation. Unfortunately, such components also dissipate significant power; thus, they need to be as far away from each other as possible to reduce component temperatures.

This article demonstrates the application of thermal prediction and design optimization to an airborne ruggedized PCB. The PCB is wedgelocked to the inside of a chassis that has externally forced convection cooled heat sink fins. Such harsh environments in terms of local ambient air temperatures, with conduction as the only predominant form of cooling, offer great challenges in achieving desired component junction temperatures.

Initial Floor Plan

The initial floor plan is shown in Figure 1. The external chassis cooling provides a cooling temperature of 35°C where the wedgelocks clamp to the PCB. The local air temperature is 75°C. Although all components dissipate heat, it is the microprocessors’ memory components that are most thermally critical.

Design Goal and Constraints

There are many differing methods of thermally managing a layout; all of them in some way control how easily the heat is dissipated from each component to the available surroundings. Ambient temperature is a factor. In this example, the interaction between two ways that promote efficient heat removal is numerically predicted by thermal prediction software.

First, the separation between the memory and microprocessor components is varied, while keeping the memory components fixed. This has a double benefit of moving the processors away from the thermal influence of the memory components, as well as moving the processors closer to the (cold) wedgelocked regions.

Second, the effect of including more densely populated arrays of thermal vias below both memory and processor components is calculated. Both are highlighted in Figure 2. The thermal vias allow heat to pass easily down to the internal metallic layers within the PCB, especially to the near full copper coverage power and ground planes, where the heat finds it much easier to conduct laterally to the cool wedgelocked sides. Without the vias, the heat experiences much more thermal resistance on its way to the wedgelocks, as it has to pass through the much lower copper coverage top signal layer.

Latest generation designs such as this one have signal frequencies now measured in GHz and signal rise times measured in pico-seconds. As such, the rise time is of the same order as the wavelength; thus, the risk of critical signal deterioration is increased. The separation between the memory and processor components, therefore, has to be as short as possible, but in this case, no longer than 11 mm.

The maximum rated junction temperature of the processors (packaged as a tape ball grid array) is 100°C. Although component suppliers do provide some data that indicate thermal performance (e.g. thermal resistance between the junction and the ambient), such data are often only applicable for a specific deployment of the package. For a real-world design such as this, with many complex, competing thermal effects, the only reliable method of accurate thermal prediction is a full 3D numerical simulation of the entire PCB assembly.

Thermal Simulation

Whereas historical simulation approaches focused on single studies to provide a pass/fail verification indication, the state-of-the-art in numerical thermal simulation can now investigate how thermal performance reacts to the changes made in the design. Such an indication allows designers to more rapidly isolate optimum combinations of design parameters to achieve a design goal.

This is achieved by first creating and simulating a Design of Experiments (DoE). The DoE is a collection of design variants constructed from combinations of changeable parameters. In this application, the DoE includes separation distance between memory and processor components, and the density of thermal vias underneath those components. In all, 20 simulations are conducted to build up a picture of the full interaction between these two parameters and the resulting (hottest) processor junction temperature.

Figure 3 shows the two extremes of the DoE. The worst thermal performance comes from the design with no thermal vias and the processor and memory components close together. The best combination includes a dense array of thermal vias under all four components, and the processor components close to the wedgelocks.

Response Surface

Twenty individual simulations provide insight into the thermal behavior of the proposed design, e.g. the actual junction temperatures of the best and worst designs, shown in Figure 3. However, a more complete picture is achieved by fitting a ‘response surface’ to the 20 simulation data points. In effect, this response surface is an advanced curve fit. It gives an overall representation of the complete interaction between changes in the design and the resulting design (thermal) performance (Figure 4).

Note the effect of thermal via density under the components is quantified as the resulting thermal conductivity down through the stackup. A value of 0.3 W/mK (thermal conductivity of FR-4) is indicative of no thermal vias. A value of around 10 indicates a highly dense array of thermal vias.

The response surface in Figure 4 confirms the more obvious of expected trends in that when the separation between memory and processor components increases, the maximum processor junction temperature decreases. Of more interest is the relationship between thermal via density and junction temperature. Regardless of separation distance, the difference in adding even a few thermal vias is notable. In comparison, further filling the space under the components with thermal vias has a reduced benefit.

A more quantified observation can be made using Figure 5. This shows various line ‘slices’ of Figure 4, in this case at various thermal via array densities. The design constraints of component separation and maximum junction temperature are also indicated as “no-go” areas of the plot. By looking at the response lines residing within the allowed design space, it is evident that some thermal vias are required with a little margin to be had by maximizing the number of thermal vias under the components.

Conclusion

By performing a number of numerical simulations using the DoE capability, followed by the creation of a response surface, an in depth understanding of the design’s response to design changes can be achieved. This leads to the more rapid balancing of design tradeoffs, as well as minimizing the risk of late design stage thermal problems being introduced because of a lack of understanding of the thermal response of a design to various changes.

The introductory example presented in this article isolates the interaction of just two design variables. In fact, this simulation methodology can be applied to any number of interacting design parameters. For example, the distance of the memory components from the wedgelock could also be varied, as could the separation of the two processors from each other. In reality, the limit of the scope of the optimization study will be set by what is under the designer’s control, and how much simulation computational resource and time are available. PCD&M

Dr. Robin Bornoff is a product manager with Flomerics. She can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..