This microreplication technique can replace photolithography and laser drilling, with little investment in training or equipment.

A list of ideal qualities required of a technology that could address the many issues facing the printed circuit fabrication industry today would contain the following:

• It would leverage existing infrastructure (capital equipment, engineering skills, materials and processes). Importantly, no new equipment or materials.
• Small-, medium- and high-volume shops could adopt it with equal ease.
• The resulting printed circuits would not require extensive requalification.
• It would address today's performance requirements (density) and provide a ready migration path to future higher densities.
• The cost of circuits could continue its rapid decline for the customer without destroying the profitability necessary for a vibrant industry.

Such a technology is available to the printed circuit industry today. Imprint patterning is an alternative fabrication approach that addresses many of the issues facing the printed circuit industry and possesses the above qualities. It results from over 15 years of development and refinement and is an elegant adaptation of technology commercially proven in other industries.

It can produce state-of-the-art circuits with significantly better yields and lower tolerances than the conventional approach. Imprint patterning can be implemented in virtually any existing multilayer printed circuit operation because it uses a subset of existing printed circuit fabrication equipment with standard materials and processes. It requires only minimal investment and no new fabrication equipment. Moreover, with imprint patterning, the existing engineering base can manufacture high-performance printed circuits with minimal training.

Background

An article in the March issue of PCD&M, "Nanotechnology and PCBs" by Michael Shores¹, does a good job of enumerating the problems facing the PCB industry. The two primary forces driving PCB requirements are 1) the continued increase of semiconductor density, and 2) cost. The following themes are extracted from Shores' article but can be found in countless other papers as well.

• There is enormous pressure on the PCB industry for:
  • finer geometries (to 50, 30, 10 µm and below)
  • better line width control
  • thinner dielectrics (to 25 µm)
  • better electrical performance
• Process costs need to be lower than current high-density solutions.
• Entry barriers for the production processes necessary to achieve these requirements should be low and allow smaller manufacturers to produce high-quality and high-density substrates.

These technology drivers and requirements have been discussed for years in the industry^2,3,4 and trade publications with the important exception of finding solutions with low entry barriers. Low barriers would allow smaller (e.g., North American) producers to participate in future industry growth with the high-volume producers. (More on this later.)

How likely are we to see solutions that meet all these criteria given the current state of the industry and trends in PCB technology?

Materials

The first solution for high-density proffered in the referenced article is to start with a material with ultra-thin copper (i.e., 2-5 µm). Thin copper foil is available today, and it does improve prospects for fine geometries and line-width control in semi-additive processes. However, the cost of the ultra-thin foil and carrier is approximately an order of magnitude higher than the cost of copper in 1 oz. copper-clad laminate or resin-coated foil (RCF). An alternative is to use a controlled etching process to reduce the thickness of more conventional foil to the 2 µm range. This, of course, is at the cost of additional processing with precise etching controls. Furthermore, use of ultra-thin foils in RCF configurations hold additional potential of incorporating the desirable properties of thin dielectrics with non-woven reinforcements. Non-woven reinforcements may be required to improve both circuit definition and electrical performance⁵ for very fine line geometries.

Another aspect of the proposed material solution would marry a thin dielectric (~25 µm) with properties that ensure control of thickness after lamination. This may be wishful thinking because the properties required for good material flow and fill to accommodate variations in circuit density work against tight tolerances in conventional approaches. And, of course, this material has yet to be invented.

In any case, as useful as a newly invented material might be, it would be insufficient by itself to propel the industry into producing cheap, dense circuits. Advanced processes are also required.

Processes

Imaging techniques - suitable for large format printed circuits - with higher resolution than today's processes are also needed. Obviously, extremely high-resolution imaging techniques are already available as is so evident in semiconductor fabrication. They resolve features some 3 to 4 orders of magnitude smaller than today's printed circuit features and are responsible in large part for the dilemma faced by the printed circuit industry. Many of these same techniques are being adapted to high-end printed circuits today. These efforts constitute one of the two major process technology trends resulting in what improvement there has been in printed circuit density - the other being laser drilled microvias. These imaging techniques include thinner liquid photoresists, step-and-repeat exposure units, glass photo tools or direct imaging systems.

In total, these techniques work well enough for small circuits that can be processed as a matrix on small panels (~355 x 405 mm) and for which higher premiums obtain. However, they seem not to be the solution for the majority of the printed circuit industry. They do not lend themselves to the large-format panels (≤ 530 x 610 mm) that are required for production throughput, efficiency and good material utilization. Although direct imaging systems do not suffer this constraint, throughput issues remain.

The cost structure tracks that of the semiconductor industry. It has very high equipment costs and a high cost of operations including the need for better clean rooms, high power and water consumption, and highly skilled engineering support. Finally, the demands of a stable process require high and continuous volumes (especially for liquid photoresists).

The second major technology trend mentioned - laser drilling - has had perhaps the biggest impact on circuit density to date. Vias in printed circuits have been shrinking to compliment reduced line widths. The industry moved to laser drilling tools when the cost-effective limits of mechanical drilling where reached at via diameters of ≥ 200 µm. The resulting HDI circuits with via diameters of 50-150 µm are now used in many high-volume, high-performance applications. The size of the smallest holes that can be laser drilled and their aspect ratios exceed what can be electroplated on most conventional printed circuit lines. This means that metallization - not hole formation - is the limiting factor now for small vias.

However, this comes at a very high capital cost for the laser. Every fabricator wishing to produce HDI circuits needs at least one laser drill costing close to half a million dollars (or subcontract the work out, which is not cost-effective.) High-volume HDI producers today can easily have over 100 laser drills. This is an enormous and growing capital requirement for the industry. Each new product generation requires more microvias and therefore more laser drills for the same throughput. It might be interesting to estimate the capital requirements for just the laser drills required to keep pace with projected interconnect density over time: a truly large number.

The advanced imaging techniques discussed above combined with laser drilling seem to be a solution for only the densest circuits on panels of limited size and available only to suppliers capable of maintaining the high capital and operational costs. The current technology trends for high-density preclude easy adoption, low-cost and low-volume operations.

A Practical Approach

Imprint patterning presents an elegant solution^6,7 to the contradictory requirements of high performance and low entry barriers. Imprint patterning replaces both photolithography and laser drilling with a simple and cost-effective microreplication step. It simultaneously forms recesses in the laminate dielectric for x-y circuit traces and holes for z-axis interconnect. It is the only known technique that produces features for traces and microvias at the same time and en masse. It averts masking and registration steps that are normally large contributors to density constraints and scrap. Importantly, it can be implemented in virtually any printed circuit shop with minimal perturbation.

Figure 1 depicts the process steps involved in imprint patterning. A two-level embossing tool is formed using normal printed circuit design data. In the simplest instantiation, embossing tools for the outer layers are inserted at the multilayer or build-up layer lamination step adjacent to the separator sheets. After lamination of the outer layers or build-up layers, the dielectric has recesses for traces and holes for vias. A standard desmear process removes dielectric material at the bottom of the vias.

FIGURE 1. The process steps typically involved in imprint patterning.

The embossed surface is metallized using standard printed circuit techniques as shown in Figure 2. The metallization process proceeds with electroless copper deposition followed by panel platting. In one method, a simple etch resist is applied to protect the recessed features during subsequent etching. The etch resist can be an inexpensive and non-photosensitive material. It self-aligns into the recesses eliminating etch resist masking and imaging steps and their associated registration issues.

FIGURE 2. The imprint patterning embossing process takes advantage of standard printed circuit techniques.

Figure 3 shows x-y traces recessed into the printed circuit dielectric and metallized. Here, the traces are plated up with 0.5 oz. copper. However, any copper thickness can be plated, including full copper fill of the trace recesses on standard electroplating lines.

FIGURE 3. The reduction/elimination of capture pads frees routing channels for vastly improved density; a) surface area, and b) a cross-section.

Large capture pads for microvias are eliminated because the imprint tool defines the geometry of traces and vias simultaneously. These geometries are perfectly reproduced during lamination, meaning imprint patterning can fabricate virtually padless vias and ensure no drill break-out. Reduction/elimination of capture pads frees routing channels for vastly improved density.

Most high-density circuits are fabricated using pattern plating. Imprint patterning uses panel plating and achieves excellent copper thickness uniformity. The embossing tool mechanically controls line width with no part-to-part variations. As a result, copper trace tolerances are lower.⁸ Following the same discussion as above, trace geometries are faithfully reproduced during lamination independent of lot, time, volume, supplier, geography, or weather. Prototypes built in a quickturn shop in North America will be exactly like the product from volume runs in Asia.

Another important advantage is that dielectric thickness is positively controlled because during lamination the embossing tools "bottom out" on layer 2 copper, as in Figure 1. This results in excellent dielectric thickness uniformity and coupled with better line definition can mean lower tolerances for impedance control.

Imprint patterning, like other microreplication techniques, is eminently capable of defining extremely fine geometries. For semiconductor fabrication, an analogous process called nanolithography is on the International Technology Roadmap for Semiconductors (ITRS) for the sub-40 nm semiconductor node. In addition, a similar microreplication technique is used to make tens of billions of CDs and DVDs per year with excellent quality at extremely low cost, and with features 3 orders of magnitude smaller than those of printed circuits.

Conclusion

Imprint patterning is now being commercialized and process guidelines will soon be available. Embossing tools are the only new entity introduced into the circuit fabrication process. Subsequent lamination, metallization and etching make use of standard processes. The elimination of photolithography and laser drilling dramatically reduces the number of process steps and their associated capital equipment and operations costs. Moreover, their classic defect rates with diminishing returns are also eliminated.

Designs using imprint patterning are already being produced with features that include 25 µm lines and spaces and with 50 µm vias on 100 µm pads. They are being produced by a low/medium-volume supplier with no new equipment or processes and using a subset of the existing process flow with minimal engineering input. The learning curve for imprint patterning is extremely high. This allows performance and cost benefits to quickly accrue to the end-users and the suppliers.   PCD&M

Dr. Craig Davidson is chief technology officer for Dimensional Imprint Technology Inc. Previously he was vice president of Technology for Multek (Flextronics). He has experience in printed circuit fabrication, card-level assembly and advanced semiconductor packaging. He holds a Ph.D. in materials science and has many patents and publications; he can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..

REFERENCES

1. M. Shores, "Nanotechnology and PCBs," PCD&M, March 2006, pg 36 ff.
2. "Emerging Directions for Packaging Technologies," Intel Technology Journal, Vol. 06, Issue 02, May 2002.
3. "Executive Summary," International Technology Roadmap for Semiconductors, 2003 Edition, 2003.
4. "2005 Research Priorities," iNEMI, November 2005.
5. G. Brist, et.al, "Woven Glass Reinforcement Patterns," PCD&M, November 2004.
6. H. Holden, "Time for a Change: Innovation in Interconnects," Circuitree, February 2003.
7. H. Holden, "Imprint Patterning, A Novel HDI Option," The Board Authority, fall 2001.
8. K. Dietz, "Fine Lines in High Yield (Part CXXV)," Circuitree, February 2006.