Design fixes that work at 'normal' board speeds can cause havoc in the 10 Gb/sec arena. Modifying the trace pair can adversely affect everything from impedance to eye diagrams.

As 10Gb/sec signaling becomes more prevalent in board design, assumptions about what affects high-speed signal transmission may no longer be true. Previously, in the sub 10Gb/sec design era, one of the key trade-offs was balancing the capability of solvers with the requirements of getting high-speed serial channels to work properly. With significant advancements in both the capacity and the usability of full-wave solvers, designers have more choices and greater flexibility for designing and analyzing interconnects. Here we will discuss how to effectively use the greater flexibility of solvers to gain more insight into the design and shorten design cycles.

One of the more interesting and popular places where solvers are being used is in package interconnects. The 3D solver was traditionally used to calculate a single channel from die to PCB, or to model sets of vias that transverse through a package in a small, constrained area. In a similar manner, 3D full-wave solvers have been used extensively to look at vias, via stubs, and connector or footprint breakout patterns at the PCB level. With the advent of more powerful 3D solvers, designers can look at multiple lanes as well as add in the package footprint or solve structures at greater mesh densities.

This investigation looks at the effects on impedance, differential S-parameters and eye diagrams when certain aspects of either the trace pair or its environment are modified. Let's first ground ourselves in the geometry of a simple package and the resulting impedances. The package we will look at is a small flip chip four-layer PBGA with all the routing on the surface layer, a partial GND plane on layer 2, a full GND plane on layer 3, and mostly solder ball pads on the bottom layer. The structures captured have a bounding box enclosing just the main target differential pair (TX6), and a larger bounding box (Figure 1) enclosing lanes TX5, TX6 and TX7 as seen from left to right (TX6 positive leg is excited at the bump).

Two common attributes to investigate when designing differential channels are the even- and odd-mode impedances of the structure. Zdifferential = 2*Zodd while Zcommon = 0.5*Zeven.

The differential impedance is of most interest because the structure will present a discontinuity to a 100 Ω differentially designed system to the extent that it deviates from 100 Ω. The impedances of the differential pairs TX5, TX6, TX7 are shown in Table 1 [PDF format]. These differential impedances and the variance between them are fairly typical when designing for a 100 Ω target differential impedance.

Variances in impedance are easily determined with a 3D quasi-static (QS) or 2D field solver. The speed of these solvers surpasses that of a full-wave solution, so they serve as a good indicator of where impedance discontinuities may exist, or where 3D full-wave finite element analysis (FEA) solvers might need to be employed. For single-ended designs, impedance discontinuities and the subsequent reflections are straightforward to calculate. However, in differential designs, and when designing at such high frequencies, impedance discontinuities cause more than just reflection. Discontinuities, such as via transitions, routing next to the edge of a package and running over a clearance hole in the plane below, can launch spurious modes or misdirect return currents that wreak havoc on your design. These additional phenomenon are not easily predictable and thus justify the need for a quality full-wave solver.

Investigating S-Parameters

One logical progression for designing gigabit channels is to look at impedance variations or discontinuities, then single-ended or differential S-parameters, and the effects on eye diagrams. If we look at TX7, we notice that without the flood region around the differential pairs, Zeven is affected while Zodd remains roughly the same. This follows, since we are not affecting the environment directly above, below or between the two legs of the differential pair. (It's worth noting that flood regions sometimes affect the positive and negative legs of a differential pair in a disproportionate manner. Their effectiveness in areas where they are not well attached to more solid GND structures is also hard to predict.)

When we remove the plane below TX7, Zodd is affected most because we are affecting the fields below both legs of the differential pair, while Zeven remains roughly the same. Moving to what this means from a differential transmission perspective, a 3D full-wave solver was used for the geometry in Figure 1 and SDD21 (differential insertion loss) was determined (Figure 2). (While the natural output of most 3D full-wave solvers is the single-ended S-parameter, recall that any N-port S-parameter set of an even number of ports can be transformed into differential transmission and reflection parameters through exciting and sensing differential and common modes - a popular practice in gigabit design.)

We can clearly see that there are significant differences in the transmitted power over frequency down to as low as a few GHz between our base case [_nopln], the case with the flood regions on the same layer as the routing removed [_nf], and the case with an additional GND plane below our differential pair [_wpln]. So, in this case modifications to the geometry first appeared as changes away from the target impedances with our QS solver, and are basically confirmed by our running of the FW solver. Differences in the SDD11 and SDD22 differential reflection parameters are significantly different from each other as well. In this case, changes in the differential pair's environment have a dramatic affect on the channel. We probably would have predicted that the plane piece below the TX7 channel would modify the impedance, but we may not have guessed that the removal of the flood region would have an impact.

So while QS solvers are good at estimating even- and odd-mode impedances and ferreting out impedance discontinuities, they can be dangerous if used for even low speed (2.5 - 3.125 Gb/sec) differential signaling. The right-hand side of Figure 2 looks at the effects of using different solvers and a finer Z-directional meshing on differential pair TX6; we again see dramatic differences in the insertion loss from bump to ball. The QS solver results [qstx6M] clearly underestimate the loss, while the initial mesh created [mmtx6] overestimates it. Two other attributes of S-parameters calculated with QS solvers are that they typically exhibit much less differential return loss, and the return loss as seen from both ends of the channel under investigation are often identical. Numerous studies show the deviation between QS and FW results happens in the 2-4 GHz range, depending on the geometry.

The change to the finer Z-directional meshing was a win for us in terms of getting more accuracy in our results for only eight additional hours of solve time; our CPU was a 3.2 GHz Pentium 4 with 2 GB of RAM. Practically, this gives us more confidence in our design, enhances our ability to meet design requirements and ultimately prevents leaving bandwidth on the table. As a designer, whenever you see several dB of difference between the results of "experiments," that should be a good indication that there will be some difference in the eye diagrams generated.

We're focusing on SDD21, which relates to differential transmission. But SDC (in practice referred to as susceptibility), SCD (in practice referred to as radiated emissions), and even SCC can also give us insight into how an interconnect is behaving. The important point is that new full-wave solvers are dramatically faster, more flexible and easier to use so there is no reason not to take advantage of them. It will pay off with greater understanding in the long run concerning 10 Gb signaling. Critically speaking, we would expect that differential transmission (SDD21) would be a very good indicator of the amount of eye opening and, perhaps, even the amount of jitter seen on the differential channel. This follows since S-parameters are really a measure of how effective a channel is in the transfer of power (or voltage) from chip to board.

Validation Through Simulation

In order to validate the significant differences in SDD21 do translate into differences in EYE diagrams, we need to employ a simulation strategy. There are several ways to create these using circuit simulators. Through a circuit simulator eye diagrams can easily be generated. The excitation we chose was a 0 nS rise/fall time pseudo-random bit stream (PRBS) of 1,024 bits in length.

In the scheme we have chosen, we will drive a differential signal and sense the differential signal out while terminating the other modes. Notice that this is going to give a relative indication of channel performance because we are only exciting and measuring from a differential perspective. By contrast, real measurements capture the effects of neighbors, and radiation loss of the channel and modes are rarely perfectly terminated. Our goal here is to test that several dB of difference in SDD21 correlate with some noticeable difference in EYE height, shape and jitter. The advantage is we can perform these simulations rapidly and vary or optimize for different data rates, rise/fall times and termination impedances among other things.

Figure 3 shows eye diagrams at the solderball/PCB interface where the differential signal would naturally be launched onto the PCB after traversing the BGA footprint or via field. The eye diagrams look "clean" mostly because the interconnect is only a few millimeters long (an extremely short trace pair) and we are only simulating 1,024 bits with a perfect edge. Even with a mostly open eye we can still notice a slight loss of amplitude and a tighter jitter tolerance when comparing the eye diagrams through the structure solved with the quasi-static solver and the structure solved in a 3D full-wave solver with no refinement (FW no refinement). We see yet another change in the eye when we add finer vertical (z-direction) meshing (FW refinement). Note that the eye diagrams exactly match what the SDD21 parameter predicted in terms of loss. That is, the quasi-static solution would be too optimistic, the 3D full-wave FEA solution without vertical refinement would be too pessimistic and the 3D FEA solution with vertical mesh refinement would fall between the two.

The last eye diagram in the lower right section of Figure 3 shows the effect of adding neighbors (TX5, TX7). While it is only a slight change, it's interesting to note that from a geometry perspective, looking at Figure 1, you would not expect the center channel to be affected at all by the TX5 and TX7 lanes. But it is - and with GND flooding supposedly shielding the channels. We are led to conclude it is likely there is coupling in the via section of the package and simulating multiple lanes for most BGA packages should be part of our strategy.

Connector Via Field Escape Routing

In this next example we will look at escaping out of a connector via field with a differential pair by coming directly out (net pair 1) and compare it with a differential pair routed out of a connector via field by weaving around obstructions (net pair 2). Net pair 1 could be a differential pair on the edge of a connector with a bend, while net pair 2 is a differential pair with purposely exaggerated routing around obstructions, likely be other plated through-holes, associated with the connector via field. In this case we've eliminated the through-hole vias being routed around for simplicity's sake. Net pair 1 is routed as microstrip on the top layer of the board. Net pair 2 is routed as microstrip also on the bottom layer of the PCB. Both differential pairs are routed with identical metal and dielectric thicknesses on the top and bottom few layers of the board so the environment is the same below both net pairs.

One end of the differential pair connects to vias that traverse the entire thickness of the board from top to bottom (2.816 mm). This PCB stack-up happens to be a 12-layer PCB with metal thicknesses of 0.01778 mm, 0.03556 mm, 0.05334 mm, 0.07112 mm and dielectric layer thicknesses of 0.508 mm, 0.1524 mm, and 0.127 mm. There are ground planes on layers 2, 4, 9 and 11. Conducting layers are assumed to be copper and the dielectric material is FR-4. The ground planes are tied together with vias near where the differential pairs begin and end as seen in Figure 4. These vias were artificially placed to provide a balanced environment and keep all variables as close as possible with the exception of the routing. In the case of net pair 1, one leg of the differential pair is slightly longer because of the bend. In the case of net pair 2 (the serpentine pair), both legs of the differential pair are the same length. Each of these structures was solved separately, although they are drawn on the top and bottom routing layers of the same PCB. Automatic tunneling around each of the sets of differential pairs allows us to easily remove excess pieces of the surrounding environment that would not contribute to the solution of the two nets acting as a differential pair.

The purpose of this exercise is to show a simple example where a FW solver can be used at the PCB level to solve for and examine S-parameters within a few hours. Also, we would like to see if these dramatically different structures result in dramatically different results. Figure 4 shows the SDD21 differential insertion loss for net pair 1 in red, and for net pair 2 in blue. The first thing that we notice is that the differential loss is considerably higher than with the package traces we evaluated in the last section. This follows since the trace lengths are noticeably longer (several inches in length), the PCBs are considerably thicker and the vias at one end of the differential pair (in the upper right-hand corner) go all the way through the board. The signals see the additional capacitive loading of the vias passing through clearance holes in the ground planes even though the ports at both ends of the differential pair are on the surface of the PCB. This additional stub and its effective capacitive loading is the likely cause for the resonance seen between 5 and 7 GHz. The other effect to notice is that although the differential pairs routing is dramatically different the SDD21 parameter looks very similar. The only noticeable distinction is the dip that occurs. Further investigation showed that the eye diagrams resulting from these two structures are dramatically different. The eye diagrams look very similar at 6.25 Gb/sec with a lot of eye opening and minimal jitter; however at 10 Gb/sec the eye for Net 2 is still very usable but the eye for Net 1 is almost completely closed. For this case it appears evident that all the discontinuities presented by the serpentine differential pair (net pair 2) is not as much a penalty as the bend in the trace and the additional length of one leg of differential pair net pair 1.

In this investigation, we have only focused on a simple four-layer PBGA package interconnect and simple escape routing from a connector pin field. Similar investigations involving 6-8 layer buildup packages, escape routing out from beneath a BGA and differential pair simulations at the PCB level have been performed in just a few hours. In the past it has been a daunting and tedious task to tackle 10 Gb/sec signaling with inflexible legacy 3D full-wave solvers. Designers today can gain a lot of insight, get their designs right the first time, stop leaving bandwidth on the table and reduce design times by:

• Using the combination of your quasi-static and full-wave solvers more strategically;
• Analyzing multiple lanes instead of single channels to avoid design failures;
• Experimenting more with geometry simplification, meshing and boundary conditions; and
• Predicting channel performance from SDD12 instead of going to simulation.

While looking at the SDD21 parameter may not predict the exact eye opening and jitter every time, it is usually a very strong indicator of performance of the link. There are also tools on the market today that that will also allow you to cascade several S-parameter blocks and get a combined result of much larger structures. Armed with a whole library of S-parameter blocks it could even make coming up with better links during design stages that much faster. Time invested in driving your full-wave solver, understanding its results and using its output in a purposeful way is almost always well spent. Successful gigabit design starts with the right tools, is enhanced with the right strategy and results in more robust designs that are right the first time without wasted effort.   PCD&M

Greg Fitzgerald is a technical specialist at Optimal Corp. in San Jose. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..