White Papers

High Speed PCB Design Considerations

by Lattice Semiconductor

The backplane is the physical interconnection where typically all electrical modules of a system converge. Complex systems rely on the wires, traces, and connectors of the backplane to handle large amounts of data at high speed. The communication between the various backplane modules depends on the inherent electrical characteristics such as impedance, capacitance, and inductance derived from connectors, trace lengths, vias, and termination, to name a few. An extremely important factor in designing a distributed-load high-performance backplane, is a basic understanding of the design practices used to ensure good signal integrity.

This technical note examines some basic differences in interconnection topologies. It describes the various issues that should be considered while designing a backplane and focuses on the critical aspects of point-to-point transmission lines that are run through a backplane. These aspects include PCB line structure, vias, device packaging and backplane connectors. A PCB design checklist is provided to aid the designer. Some frequency specific discussion and guidelines are given. This document also discusses Lattice Semiconductor's FPGA product line and its SERDES high-speed backplane interfaces. These provide high speed serial streams through CML differential buffers.

High Speed Digital Design Principles

by Satish Venkataramni, technical marketing engineer, Intel

All embedded Intel architecture products vary in their uses, but they have one thing in common: the complexity of their design. From an engineer’s perspective there are many new and unfamiliar challenges of getting large amounts of electrical, electronic hardware on generally a smaller piece of board/PCB in the case of embedded design. This white paper discusses some of the major factors that need to be considered in designing an embedded product and the various high speed digital design concepts that play a vital role in the functionality of the hardware/ product as a whole. This paper will help a designer understand why the electrical signals act so differently on a high speed design, identify the various problems that may occur in the design, and solve these problems.

 

"Copper Foil Weight vs. Thickness"

by Stanley L. Bentley, Divsys


Abstract: The copper foil on the printed circuit board has two very confusing units of measure. These
units are frequently mixed and confused for one another.

Published November 2012


"Sequential Lamination"

by Stanley L. Bentley, Divsys

Abstract: Sequential lamination is necessary when the design of the interconnect system has connections that are not required on all layers or that if made available on all layers would impact the system performance or create an unsolvable congestion in the design.

Published May 2012

The Value of PCB Manufacturing Quality During Prototype: You Get More Than You Pay For

by Nolan Johnson, CAD/EDA manager, Sunstone Circuits

Design flows are a key contributor to the efficiency of the electronic product development cycle. But one needs to look a little deeper to realize that the prototype fabrication portion of the process is of critical importance in catching design errors early and effectively. It is the prototype hardware, after all, which verifies the original design intent embodied by the CAD file contents; the relationship is symbiotic.

 

Amkor Converting to Pin-Gate Molding Process to Meet Industry Low Cost Demand

by Amkor

Pin-gate molding structures are said to provide superior quality, reliability and performance, and can be less expensive than traditional corner gate molding. Amkor’s PGM process is designed with a JEDEC-compliant larger mold cap which has a number of benefits, including allowing the routing of active traces and vias within the mold cap dimensions, improving protection from solder mask cracking, and facilitating larger die sizes in the same form factor. In addition, Amkor’s PGM PBGA uses a package saw singulation process which produces a smoother edge on the package, reducing the potential for binding in the test socket and shipping tray, and thus delivering higher yields.

PGM is also a more cost-effective PBGA structure as it uses higher density substrates and smaller diameter wire than traditional corner gate molding. Gold wire diameter can be reduced by over 50% down to 0.5 millimeters.  Copper wire diameters can also be reduced significantly. These capabilities also extend the usefulness of wirebonding to smaller silicon nodes. With PGM, wirebonding can now be used down to 28 nm.

The white paper describes the package, the process, reasons for the change and the current state of volume production.

"FPGA-Controlled Test (FCT): What It Is and Why It Is Needed"

By Al Couch, Asset InterTech chief technologist for core instrumentation

This white paper describes a new method for validating, testing and debugging circuit boards by embedding a board-tester-in-a-chip. The method, known as FPGA-controlled test (FCT), involves the automatic insertion of multiple embedded instruments into a field programmable gate array (FPGA) to function as a board tester. The embedded board tester is then operated from an intuitive drag-and-drop graphical user interface.

The board-tester-in-a-chip does not require a dedicated FPGA. The inserted tester can be easily removed once it has completed its tasks and reinserted later if needed again. Or, some or all of the tester may remain embedded in the system throughout its life cycle.

Because of significantly escalating gate densities, FPGAs are an effective platform for embedded test and measurement functionality at a time when legacy external probe-based equipment like oscilloscope and in-circuit test (ICT) systems are providing less and less test coverage. Faster speeds and greater complexities have increased the electrical sensitivities of chips and boards to the point where a physical probe will not provide adequate test coverage or reliable results.

 

 

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