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Cadence Issues Call for Presentations for CDNLive Silicon Valley

Published: 11 December 2017
 by Chelsey Drysdale

SANTA CLARA – Cadence issued a call for presentations for CDNLive Silicon Valley, taking place here Apr. 10-11.

Possible conference topics include mastering advanced-node design challenges; addressing automotive design requirements; accelerating SoC integration with Interface IP; software-driven verification; designing in DDR memory; analog/mixed-signal SoC verification; simplifying functional verification with verification IP; PCB design for manufacturing and testability; PCB high-density interconnect (HDI) and flex designs; silicon photonics; low-power design and verification considerations; digital design and full-flow correlation; and vision processing.

To submit an abstract, visit https://www.cadence.com/content/cadence-www/global/en_US/home/cdnlive/silicon-valley-2018/call-for-presentations.html?CMP=CDNLiveSV_EM_MKTO_120617&mkt_tok=eyJpIjoiWmpsbE1EaGtObUpoWXpNeSIsInQiOiJxUXlvSlwvbFBVWDZhY3lZcG13endcL0ZBRlhNVEJaYzA2bzR6SGNiZ0V4dGI4TzI5QVhjUXJCWTl4aTd3bkNZNUpxNEd6TTRic3hFYnV5Z2JScE0xQkJNVHlnYzRxQm8yM05NczNGY0ZYMkdwVTRnVk93ZWhIaEhGWDlWNUtVQndHIn0=.

Abstracts are due Feb. 2.

 

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