SANTA CLARA, CA – Cadence is accepting abstracts for CDNLive Silicon Valley, which will take place Apr. 11-12 at the Santa Clara Convention Center.
Suggested topics include mastering advanced-node design challenges; addressing automotive design requirements; accelerating SoC integration with Interface IP; software-driven verification; designing in DDR memory; analog/mixed-signal SoC verification; simplifying functional verification with verification IP; PCB design for manufacturing and testability; PCB high-density interconnect (HDI) and flex designs; silicon photonics; low-power design and verification considerations; digital design and full-flow correlation, and vision processing.
To submit an abstract, visit https://www.cadence.com/cdnlive/na/2017/Pages/cfp.aspx?CDNLiveSV_EM_MKTO_121216&mkt_tok=eyJpIjoiTURnMlpqSXlaV1EzTVRVeCIsInQiOiJuZ1l6RHVBRUVaZE93WkI0bGw3a3hyVUJLQmhZanpcL2RpMFJPXC8zUGdTUklNelJ5cTZyVGVVVEFwUUJRcDB1V2lQV3NkcHA3SGtNbGtOZkJFUzlHek5FTElpNThGZkhoWktaZU9ZNE9HT2lGcG1Pdm13QVlRMjd6Y3c3Q3dKMW90In0%3D.
The deadline for abstracts is Jan. 27.