HyperLynx printed circuit board simulation software now performs end-to-end, fully automated serializer/deserializer (SerDes) channel validation.

Provides tool-embedded protocol-specific channel compliance. Provides embedded protocol expertise for PCIe Gen3/4, USB 3.1, and COM-based technology for Ethernet and Optical Implementers Forum (OIF). Performs equalization optimization (CTLE, FFE, DFE) based on protocol architecture and constraints. 3D explorer feature for design and layout optimization of non-uniform structures like breakouts and vias. Provides channel structure design and pre-layout optimization. Template-based 3D structure synthesis can be used for differential pair, BGA breakouts, via configurations, series-blocking capacitors, and more.



Mentor Hyperlynx web

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