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Features

A special panel discusses the growth of AI tools and its possible effects on the industry.

“Will AI take my job?”

That’s the question on the mind of many around the world today – including electronics engineers and PCB design engineers – and was one of several questions considered during an online panel hosted by PCEA in March.

A group of panelists with notable AI experience – Circuit Mind’s Tomide Adesanmi, Cadence Design Systems’ Taylor Hogan, Zuken’s Kyle Miller, Luminovo’s Sebastian Schaal and Siemens Digital Industries’ David Wiens – gathered to share predictions for the future of AI in the electronics supply chain and answer questions from an audience of industry professionals.

HDP is embarking on new rounds of evaluations of laminates and lead-free solders.

The High-Density Packaging User Group, the nonprofit consortium of electronics manufacturers and suppliers that collaborate on various technical problems in order to reduce cost and time to market, has nearly 25 projects underway, several of which are due to be completed this year.

We spoke in March with Madan Jagernauth, marketing director and project facilitator of HDP, about its current research on lead-free solder alloys, its recent conference Best Papers, and whether the consortium members are ready to tackle artificial intelligence.

Adding thermal vias can take up valuable board space with little benefit.

We have developed several articles and publications in the past questioning the value of thermal vias.¹ Here is our definitive conclusion, and why.

Thermal vias are non-current-carrying vias between two layers provided for the purpose of permitting heat to conduct from one layer in a PCB to another. The idea is to lower the temperature of the heated surface compared to another, lower temperature surface. In a typical application, the heated surface might be a pad underneath a heated component. The opposite surface might be another pad or plane further down in the PCB structure. Someone untrained in heat transfer might suggest using thermal vias without an opposite copper surface, but we will show that such an approach is totally ineffective.

Building and maintaining what's said to be the world's largest CAD database requires strong relationships.

Keeping up with the increasing demand for new and specialized components is no easy task, but Ultra Librarian's team has proven up to the task – to the tune of more than 16 million components in its library and a quarter of a million unique downloads per month.

When we visited Ultra Librarian's office in Huntsville, AL, in early December, EMA Design Automation had just announced the library service's spinoff into a new ECAD-oriented company, Accelerated Designs, which was the original name of the company under its founder, Frank Frank, before it was acquired by EMA in 2016.

Coating traces or filling vias is usually a wasted expense.

We are often dismayed by the number of individuals (and especially board manufacturers) who suggest that coating a trace or filling a via cavity can result in significant thermal and/or electrical conductivity improvements. Herein we will try to explain why, in almost all cases, this is not true.

Individual trace coatings. Often users (especially board manufacturers) suggest trace thermal or electrical conductivity can be improved by coating the trace with some conducting material. It sort of makes intuitive sense that additional material can provide more benefit. Trace coatings are typically limited in a practical sense to plated copper or a solder coat. We suggest that such a coating can be analyzed by looking at the separate elements (bare trace and coating) as two parallel conductors.

Models for understanding sources, quantification and mitigation of crosstalk.

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. It is caused by unwanted coupling between signal links and between signal links and power distribution systems. The effect is deterministic, but very difficult to predict in many cases – too many variables and uncertainties. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known and just guessed.

A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. On top of that, distortions caused by crosstalk cannot be corrected by signal conditioning techniques at the receiver side. Thus, it is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently. This is the first part of the paper with an overview of crosstalk sources and terminology – just a slice through the complicated phenomenon. The second part will describe and compare different ways to quantify, compute and measure crosstalk. This paper continues the "How Interconnects Work" series.^1-4