DC Analysis of PDN: Essential for the Digital Designer
DC analysis of a power delivery network, commonly referred to as IR drop, DC power integrity, or PI-DC, answers fundamental questions that every digital (or analog) designer should have. Optimizing the PDN can save precious design real estate and layers, resulting in lower cost with increased performance and reliability.
by Jeff Loyer
Via-in-Pad Design Considerations for Bottom Terminated Components on Printed Circuit Board Assemblies
With their small component body footprint and minimal PCB area requirements, physical designers are keen to incorporate small footprint QFNs to meet a variety of voltage/power regulation, logic controller and clocking needs. Methods for filled thermal via design points to ensure a planar surface upon which to solder the component to the thermal pad – including solder mask via tenting, encroached vias, and via-in-pad plated over – bring manufacturability trade-offs, reliability, and cost impacts. A new alternative using QFNs with open thermal via-in-pad (VIP) structures uses conventional PCB through-hole via technology that is not plugged nor filled in any manner, ensures proper via sizes/pitch/counts/locations are achieved, and incorporates custom solder mask window patterns overtop copper thermal pad areas.
by Matt Kelly, Mark Jeanson and Mitch Ferrill