Will ASICs and memory be packaged side-by-side? 

The annual ECTC revealed exciting advancements on single- and multi-die packages.

The IEEE Electronics Components and Technology Conference (ECTC) at the end of May welcomed nearly 1,500 attendees to the sunshine state of Florida to discuss the latest developments in electronics packaging technology.

A panel discussion on the first evening focused on the topic Panel Fan-Out Manufacturing: Why, When and How? The panel was designed as a jury, with a customer (Qualcomm) surrounded by round wafer proponents (TSMC, Amkor’s Nanium) on one side and panel proponents (Deca Technologies, IZM Fraunhofer consortium) on the other. No conclusion was reached regarding the “right” path to meet customer requests for lower-cost packaging (in this case Qualcomm), but clearly panel processing could be an option. Exactly when panels would move into high-volume manufacturing remained a mystery, but in the audience representatives from Samsung Electro-Mechanics (SEMCO) watched carefully for the reaction. SEMCO continues its development of a panel line, while Nepes and Powertech Technology (PTI) indicate lines are ready. Unimicron continues its research on panel processing and presented a paper discussing stress and warpage for its RDL-first panel FO-WLP.