Multi-Fabric Planning for Efficient PCB Design
Traditional methodology for chip-package-board design has been a serial top-down flow where the chip drives package connectivity and, in turn, the package drives board connectivity. This approach worked when the largest device on a PCB was still well under 1,000 pins and the matrix was three to four rows deep. With more functional integration taking place at the chip- and package-level, package pin counts continue to grow to a point where several thousand pin packages will not be uncommon. Coordinated planning requires changes to methodology and tools and flows capable of delivering a simultaneous access to domain-specific data.
by Kevin Rinebold
Reducing Stencil Wipe Frequency
Do nanocoatings really extend stencil underwipe intervals? As part of a stencil study, two nanocoated fine-grain stencils were evaluated using a complex test vehicle. The investigators expected a tenfold extension of wipe intervals would show a definite decline in print quality. The results were amazing – and unexpected.
by Chrys Shea and Ray Whittier
Facts About OSHA’s New Hazard Communication Standards and GHS
How the Global Harmonized System (GHS) impacts US, Mexico and Canada.
by Lindsey Shehan and Kevin Pawlowski