Addressing ‘Power-Aware’ Challenges of Memory Interface Designs
Memory interfaces are challenging signal integrity engineers from the chip level to the package, to the board, and across multiple boards. As the latest DDR3 and DDR4 speeds support multi-gigabit parallel bus interfaces with voltage swings smaller than previous generation interfaces, there is no room for error in any modern memory interface design. The combination of complete model libraries, advanced tools and engineering expertise addresses modern buses and data rates.
by Ken Willis and Brad Brim
Lead-Free Assembly Design for Manufacturability Considerations
The changeover to lead-free has brought with it serious implications for many key design rules. A look at the system-level management requirements and key DfM elements shown to improve overall yield, quality and reliability of high-complexity, high-reliability hardware.
by Matt Kelly and Mark Hoffmeyer, PH.D.
Availability Index and Minimized Reliability Costs
A model for quantifying how the total cost of improving and maintaining reliability can be minimized, and the relationship of that minimized cost to the availability index.
by Ephraim Suhir, Ph.D., and Laurent Bechou, PH.D.
How Much Protection Is Enough?
Five questions to ask concerning ESD protection.
by The ESD Association
W. Scott Fillebrown
Reducing flex assembly thickness.
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