October 2010 Cover


Generalized I/O Timing Analysis
SI/timing analysis can be performed heuristically, but there is a systematic approach as well. Timing analysis can be performed to create PCB layout design trace length constraints (pre-layout analysis), to determine the maximum data rate where the interface is still reliably operational (pre- or post-layout), and to verify an already routed board (post-layout analysis) would work reliably.
by Istvan Nagy

Team Design
No Reassembly Required
Introducing parallelism into the design process shortens, accelerates or recovers our schedules. The approaches to concurrent engineering. 
by Jamie Metcalfe

Perfect Paperwork
Best Practices for Preparing Documentation
Electronics assembly documentation includes files such as design schematics, assembly drawings, test procedures, BoMs and more. Problems or omissions in this documentation result in delays and, in extreme cases, may lead to product deficiencies and quality issues. How to ensure documentation for the EMS company is accurate. 
by George Henning



  • Caveat Lector
    Still like Ike?
    Mike Buetow

  • Talking Heads
    Altium’s Alan Smith.
    Mike Buetow and Chelsey Drysdale


  • Global Sourcing
    What DoD cuts mean for the US PCB industry.
    Matthew Holzmann

  • ROI
    Do customers know what they want?
    Peter Bigelow



  • Designer's Notebook
    Optimizing FPGA-to-board connectivity.
    Duane Benson

  • Final Finishes
    Giving you the ‘creep.’
    Lenora Toscano

  • Tech Tips
    Digital pre-distortion.
    ACI Technologies Inc.
  • Technical Abstracts
    In case you missed it.

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