Pinning down FPGA/PCB integration.
Present day field-programmable gate arrays (FPGAs) are fast and provide excellent ways to develop advanced products. They have interface speeds reaching many Gbps and can replace traditional application specific integrated circuit (ASIC) technology by incorporating embedded processors, digital signal processor (DSP) cores and memory systems.
As its complexity increases, the challenge of implementing an FPGA on a printed circuit board (PCB) has become a daunting task. Some of the larger devices have nearly 2000 pins in a fully populated ball grid array (BGA) package. The smaller devices are often used in clusters of multiple FPGAs, which also pose a challenge. Frequent use of advanced (complex) memory standards, such as DDR3, further complicates the FPGA/PCB integration.
Traditional pin swapping, as well as swapping defined pin groups or banks, is not practical as the swappability of an FPGA is both device- and application-dependant. At the same time, it is frequently in flux during PCB design. Manual- or script-based methods of FPGA/PCB integration are seriously outdated. Companies can struggle for months with the pin assignment for a single FPGA/PCB integration, resulting in a critical bottleneck. What’s needed is an integrated FPGA/PCB co-design flow.
The over-the-wall flow needs to be revisited. By bringing FPGA and PCB designers together in a common environment, the impact of a change in one domain becomes visible in the other, and vice versa.
Nearly everyone uses the FPGA vendors’ design tools in one form or another, but these tools are not necessarily PCB-aware. Inevitably, every FPGA will end up on a PCB, resulting in an overcomplicated design with excessive layers– as well as a struggle to reach acceptable signal integrity.
FPGA pins must be assigned in a way that is optimal to the PCB in terms of the ability to break out the FPGA signals on a few layers and the number of vias, interconnect length and resulting signal quality. Unfortunately, we cannot randomly assign signals. The swappability of pins is device- and application- dependant.
We could manually set up swap rules, but this would be a monumental exercise, especially when considering the multitude of pin and bank assignment rules that come with the latest circuits. For example, moving a signal from one pin to the next may look harmless but can actually cause FPGA timing failures. We need to follow a large set of FPGA vendor and device rules and create corresponding place and route and synthesis constraint files for the FPGA. In addition, the pin assignment process includes selecting a proper I/O standard, sufficient drive strengths and termination requirements. Because the FPGA/PCB integration is in the critical path for the design, we need to look for methods to change the serial process into a concurrent process that saves as much time as possible.
We can start the pin assignment process as soon as the FPGA designer can supply an HDL entity (VHDL) or module (Verilog) declaration file. We can use this data to create a preliminary signals list and automatically create a schematic symbol and start connecting the FPGA. As this takes place, the FPGA can be simulated and synthesized, allowing it and the system design to progress in parallel. Both designers can cooperate in creating pin assignments.
There will likely be a few iterations where the pin assignment will be altered, so this process step can also be used to update the symbols and the schematic to save you from manual clean up. A key element in the process is to monitor all the data files involved and manage synchronizing both FPGA and PCB as data changes. A form of data management that monitors changes in combination with a data synchronization wizard is used to manage consistency between the FPGA and the PCB flow.
We cannot just look at the design’s component pins during assignment and optimization. If you read BGA Breakouts and Routing, Effective Design Methods for Very Large BGA by Charles Pfeil, you understand how the complex breakout patterns result in a completely different pin ordering. Therefore, we must also take into account breakouts and pre-routes. Also, further pin swapping might be needed as the design progresses. In an integrated FPGA/PCB flow, such operations will be made true to the device and the application-specific swapping rules.
As many modern FPGAs operate with extremely high data rates, it is vital to have fast access to signal and power integrity (SI/PI) tools that are easy to set up and can be used by the everyday designer to validate the optimization result in the SI/PI domain.
Finally, the FPGA designer must run a final simulation and place and route operation to complete the design. While manual methods are still common, it’s clear that today, a completely integrated design flow is required to be able to reach design closure within a realistic timeframe and to hit performance and cost targets.