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Written by Per Viklund   
Friday, 29 June 2012 21:50

The infrastructure to support embedding all component types is now in place.

Starting to work with a new PCB technology is exciting – almost (I imagine) like commanding the Starship Enterprise and boldly going where none has gone before. It’s daring to take risks needed to reach such goals. However, in many a business climate, it’s not always wise to be that bold. Fortunately, most of us don’t have to go where none has gone before, but just where “only few” have gone before.

What I’m getting at is the enabling technology known as embedded active parts and how to deploy it without having to boldly go and make all the mistakes yourself. That is a major difference: In the embedded universe, you are not alone, and the infrastructure is now in place to help mitigate the risks.

Some years ago we listed the business drivers for using embedded passives (EP) on a PCB.

We looked at total cost savings: design costs, supply chain costs, assembly costs, etc. We looked at saving board space so we could add more functionality per unit area. We looked at increasing product performance by limiting circuit parasitic effects. In some cases, we looked at the technology as a product enabler: being able to build something that otherwise would not be possible. Behind these drivers is the fact that consumer products – a huge market – match these drivers perfectly: cheaper, faster, smaller.

However, other means to do “cheaper, faster, smaller” came into fashion before EP got widely adopted. There is, of course, still a desire to make the next product perform faster, have more functionality, in a smaller form factor – and cost less to design.

Embedded packaging. One solution is to again look at embedding, but this time, embed everything. Active and passive parts can now be embedded within the layers of a PCB. This includes bare die, SMD parts, and possibly integral passives. Parts are embedded in the dielectric layers between innerlayers and are connected by microvias from the adjacent metal layers. We call this technology ECP, for Embedded Component Packaging. Looking at the ECP module in Figure 1, one might conclude it is only for IC packaging. That is far from correct: ECP is much more versatile.



The business drivers mentioned make a perfect match for ECP, so the potential gain is very high, but the stakes are also high. Again, there is this thing about the risks and “boldly going.”

Several industry/academic consortia are working to make ECP available. Instead of just developing the technology, these organizations have put enormous focus on the supply chain and practical deployment of ECP. One lesson we’ve learned has been that everyone involved must work together for success. In Europe, the HERMES project led by AT&S and financially supported by the European Community started in 2008 and has led to an ECP process that is based on standard PCB fabrication and assembly processes. In the US, Georgia Tech heads the EMAP-II project (EMAP, or Embedded Active and Passive modules). EMAP focuses on thin-film based modules where the silicon is assembled after the substrate has been manufactured.

Both projects include industry partners from across the supply chain. For those interested in ECP, these consortia are an exceptionally good point to start.

Challenges with embedding. As with all new technologies, there are challenges to be addressed, and good solutions are key to technology adoption. This is where everyone involved must work together.

For example, very few CAD tools really support ECP today, and this leads to workarounds where the design rule checks (DRC) might not work. Yet with this level of complexity, DRC is more important than ever. Some tools require adding dummy layers that could significantly complicate via management.

Manufacturing data is another critical area. We used to send the board shop Gerber files and various drawings and text documents to clarify what we intended to build. Today, we can use intelligent data formats that no longer make assumptions about parts being assembled on outer layers only.

With silicon embedded in the board, the cost of a scrapped design is very high, so we must eliminate any situation where intent is up to interpretation. These are good examples where an EDA vendor and an ECP manufacturer work together with customers to ensure that the design process is properly supported throughout the design flow tools and that manufacturing data are 100% explicit.

It certainly will be interesting to follow the adoption of ECP in the industry.

Per Viklund is director of IC Packaging & RF at Mentor Graphics (mentor.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Saturday, 30 June 2012 00:05
 

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