| Hitachi Claims 40% Cut in Design Time |
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| Tuesday, 30 June 2009 10:37 | |||
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SAN JOSE, CA and TOKYO – As part of its companywide initiative to reduce design cycle time and improve efficiency, Hitachi Ltd. has employed Cadence Design Systems’ Global Route Environment (GRE) technology for Allegro PCB design. Hitachi reports the measure has reduced PCB place-and-route design time by 40% for high-speed communication products. The company used the GRE technology on its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where automation had not been previously available. Hitachi feels the technology will also be effective for other PCB design challenges, such as engineering changes and routing estimation. It plans to use GRE as a standard solution throughout the design environment. GRE technology provides automaton for various stages of interconnect planning and routing where no automation has been available.
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| Last Updated on Tuesday, 30 June 2009 11:35 |
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Products
Mentor Graphics Introduces FloTherm IC
FloTherm software is for IC thermal characterization and design. Is a Web-based platform that automates design tasks associated with full-spectrum thermal characterization and validation. Is said to reduce time spent on thermal characterization and design by up to 25% by providing an automated process that includes pre-verified thermal models. Addresses full-spectrum thermal metric and compact model generation with adherence to JEDEC standards; package-aware parametric design for what-if analysis; EDA tool interfacing for detailed modeling of BGA substrates for physical layout, and data...
FloTherm software is for IC thermal characterization and design. Is a Web-based platform that automates design tasks associated with full-spectrum thermal characterization and validation. Is said to reduce time spent on thermal characterization and design by up to 25% by providing an automated process that includes pre-verified thermal models. Addresses full-spectrum thermal metric and compact model generation with adherence to JEDEC standards; package-aware parametric design for what-if analysis; EDA tool interfacing for detailed modeling of BGA substrates for physical layout, and data...
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Printing Screens Revisited
Research continues on improving printed frontside silver conductor line efficiency.A simple Internet search will reveal the photovoltaic industry is working hard on higher aspect ratio frontside conductor grids as a route to greater solar cell efficiencies. This is because the conductors, typically screen-printed on a cell’s frontside, block sunlight from reaching the energy converting strata below, and the narrower they are, the less shadow they cast. However, as it is essential they...
Research continues on improving printed frontside silver conductor line efficiency.A simple Internet search will reveal the photovoltaic industry is working hard on higher aspect ratio frontside conductor grids as a route to greater solar cell efficiencies. This is because the conductors, typically screen-printed on a cell’s frontside, block sunlight from reaching the energy converting strata below, and the narrower they are, the less shadow they cast. However, as it is essential they...
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