When it comes to power distribution network design, put your trust in analysis.

It's like a religion," Steve Weir, consultant with Teraspeed Consulting Group said. "There are fundamentalists and devoted followers in different camps." Weir, a widely acclaimed signal integrity icon, is referring to design strategies for the power distribution network (PDN).

Just like religion, some principles concerning the PDN are widely agreed upon and some are mired in controversy. What everyone agrees on is the role of the PDN: to distribute the power and ground with an acceptable level of rail noise, typically less than 5%, for core logic switching, I/O switching and internal signal layer transition switching.

This translates into keeping the impedance of the PDN, as seen by the chip, below a target value. With core voltages approaching 1V and currents of 10 A or more, the impedance of the PDN must often be below 5 mΩ, up to the hundreds of MHz frequency range. At 100 MHz, this means keeping the loop inductance of the PDN below 10 pH. This is why, says Weir, "The three most important features in the PDN are inductance, inductance and inductance, and enough capacitance is needed to take care of low frequencies."

It is agreed that the way to design the PDN is to start with the right voltage regulator module (VRM). This will establish a low impedance from DC to some low frequency range, often as low as 2 kHz. Above this frequency the bypass capacitor network takes over. At 2 kHz 5 mΩ requires over 10,000F, often more than a VRM can support.

At the high frequency end, the package or circuit board resonance affects limit PDN performance. Most agree that designing the PDN over this range of a few kHz to hundreds of MHz is about using capacitors and proper board design to provide low impedance. The religious fervor is over the best way of selecting the capacitors and placing them on the board.

If you are looking for answers to these and other questions, one of the best resources is the Web site of X2Y (X2Y.com), a new type of ultra-low inductance capacitor technology. There you can find many of Weir's papers as well as dozens of others on capacitor performance and PDN design principles.

In a paper at DesignCon this year, Weir analyzed the three different approaches for selecting capacitor values for the PDN: The big V, where typically the largest value of capacitance for a given package size is used; the multi-pole approach, where one capacitance value per decade of capacitance value is selected; and the many pole approach, where typically three different capacitance values per decade are selected.

These approaches provide a different impedance profile (FIGURE 1), and interact differently with the VRM at the low end, and the board resonances at the high end.

Which is the "right" one? According to Weir, it depends. "Viable bypass capacitor networks may be synthesized by any of the three popular techniques using straightforward spreadsheets backed by SPICE simulations. The real key is to focus on the phase of the overall system."

The big V affords the greatest simplicity for meeting impedance magnitude over a given frequency range, and is the most robust to manufacturing variations and errors. The multi- and many-pole methods yield different phase responses. "They provide one way to tame sometimes deadly resonances," Weir said.

Another question addressed by Weir is, Does position matter? The answer again is, It depends. In a presentation created last year, Weir goes further to identify the deciding criteria. The impact from the position of the decoupling capacitors depends on the capacitor's attached inductance, compared to the spreading inductance in the planes. "Until we get into wave effects of the packaging, it is really all about an inductance budget," Weir said. If the PCB spreading inductance is a small amount of that budget, capacitor position is not important. "But in high performance systems, the PCB spreading inductance is almost always a big factor," he said.

For capacitors on the same side of the PCB as the BGA and common BGA power chevrons this means, " ... for positions up to 0.5" from the BGA perimeter, the PCB inductance changes little and the position is not critical. But if the PCB consumes too much of the inductance budget, required capacitor counts grow exponentially."

The debate on the optimum design approach for the PDN arises because there are multiple right answers, depending on the specific set of tradeoffs in required performance, risk, cost and corporate history. Unlike religious questions, deciding on the right PDN approach for your design is not about faith, but analysis.   PCD&M

Dr. Eric Bogatin is president of Bogatin Enterprises (bethesignal.com). He is author of Signal Integrity - Simplified; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .